Package structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10636775-B2
Application number	US-201715795280-A
Country	US
Kind code	B2
Filing date	Oct 27, 2017
Priority date	Oct 27, 2017
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

First claim

What is claimed is:

1. A package structure, comprising:
a first package, comprising:
at least one first semiconductor die, encapsulated in an insulating encapsulation; and
through insulator vias, electrically connected to the at least one first semiconductor die, wherein the through insulator vias are encapsulated in the insulating encapsulation;

a second package, located on the first package, comprising:
at least one second semiconductor die; and
conductive pads, electrically connected to the at least one second semiconductor die; and

solder joints, located between the first package and the second package, wherein the first package and the second package are electrically connected through the solder joints;
an underfill, located between the first package and the second package, wherein the solder joints are encapsulated in the underfill, and a sidewall of the second package is covered by the underfill, and
wherein a maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction,
wherein a maximum size of a surface of one of the solder joints physically contacting a surface of a respective one of the conductive pads is greater than a maximum size of the surface of the respective one of the conductive pads.

2. The package structure of claim 1 , wherein a ratio of the maximum size of the solder joints to the maximum size of the through insulator vias is greater than or substantially equal to 1.1 and less than or substantially equal to 2.

3. The package structure of claim 1 , wherein a ratio of the maximum size of the solder joints to the maximum size of the conductive pads is greater than or substantially equal to 1.1 and less than or substantially equal to 1.6.

4. The package structure of claim 1 , wherein the maximum size of the conductive pads is substantially equal to the maximum size of the through insulator vias.

5. The package structure of claim 4 , wherein each of the solder joints has a first contact surface, a second contact surface opposite to the first contact surface and a side surface connecting the first and second contact surfaces, wherein the first contact surface of the solder joint is connected to one of the conductive pads and the second contact surface of the solder joint is connected to one of the through insulator vias, and an area of the first contact surface is substantially equal to an area of the second contact surface.

6. The package structure of claim 4 , wherein each of the solder joints has a first contact surface, a second contact surface opposite to the first contact surface and a side surface connecting the first and second contact surfaces, wherein the first contact surface of the solder joint is connected to one of the conductive pads and the second contact surface of the solder joint is connected to one of the through insulator vias, and an area of the first contact surface is greater than an area of the second contact surface.

7. The package structure of claim 1 , wherein an interface of a vertical cross-section of the solder joints and the underfill is a curved surface.

8. The package structure of claim 7 , wherein a portion of each of the through insulator vias are free of the insulating encapsulation and wrapped by the underfill.

9. The package structure of claim 8 , wherein an interface of a vertical cross-section of the portion of each of the through insulator vias being free of the insulating encapsulation and wrapped by the underfill is a planar surface.

10. A package structure, comprising:
a first package, comprising:
at least one first semiconductor die, encapsulated in an insulating encapsulation; and
through insulator vias, electrically connected to the at least one first semiconductor die, wherein each of the through insulator vias is partially covered by the insulating encapsulation with a portion exposed and protruded out of the insulating encapsulation with a distance;

a second package, located on the first package, comprising:
at least one second semiconductor die; and
conductive pads, electrically connected to the at least one second semiconductor die;

solder joints, located between the first package and the second package, wherein the first package and the second package are electrically connected through the solder joints;
an underfill, located between the first package and the second package, wherein sidewalls of the solder joints and a sidewall of the portion of each of the through insulator vias exposed by and protruded out of the insulating encapsulation are directly covered by the underfill, and a sidewall of the second package is covered by the underfill, and
wherein a cross-sectional area of the solder joints is greater than a cross-sectional area of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a cross-sectional area of the conductive pads measuring along the horizontal direction,
wherein a maximum size of a surface of one of the solder joints physically contacting a surface of a respective one of the conductive pads is greater than a maximum size of the surface of the respective one of the conductive pads.

11. The package structure of claim 10 , wherein a ratio of the cross-sectional area of the solder joints to the cross-sectional area of the through insulator vias is greater than or substantially equal to 1 and less than or substantially equal to 1.5.

12. The package structure of claim 10 , wherein a ratio of the cross-sectional area of the solder joints to the cross-sectional area of the conductive pads is greater than or substantially equal to 1 and less than or substantially equal to 1.5.

13. The package structure of claim 10 , wherein the cross-sectional area of the conductive pads is substantially equal to the cross-sectional area of the through insulator vias.

14. The package structure of claim 13 , wherein each of the solder joints has a first contact surface, a second contact surface opposite to the first contact surface and a side surface connecting the first and second contact surfaces, wherein the first contact surface of the solder joint is connected to one of the conductive pads and the second contact surface of the solder joint is connected to one of the through insulator vias, and an area of the first contact surface is substantially equal to an area of the second contact surface.

15. The package structure of claim 14 , wherein an interface of a vertical cross-section of the solder joints and the underfill is a curved surface, and an interface of a vertical cross-section of the exposed portion of the through insulator vias and the underfill is a planar surface.

16. The package structure of claim 13 , wherein each of the solder joints has a first contact surface, a second contact surface opposite to the first contact surface and a side surface connecting the first and second contact surfaces, wherein the first surface of the solder joint is connected to one of the conductive pads and the second contact surface of the solder joint is connected to one of the through insulator vias, and an area of the first contact surface is greater than an area of the second contact surface.

17. The package structure of claim 16 , wherein an interface of a vertical cross-section of the solder joints and the underfill is a curved surface, and an interface of a vertical cross-section of the exposed portion of the through insulator vias and the

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Wei-Yu
• Su An-Jhih
• Wu Chi-Hsi
• Yeh Der-Chyang
• Huang Li-Hsien
• Tsai Po-Hao
• Yeh Ming-Shih
• Liu Ta-Wei

Classifications

• H01L2225/06568

  Electricity · mapped topic

• H01L2221/68359

  Electricity · mapped topic

• H01L2221/68345

  Electricity · mapped topic

• H01L2224/48227

  Electricity · mapped topic

• H01L23/3121

  Electricity · mapped topic