Semiconductor arrangement and method for making

Patent metadata

Field	Value
Publication number	US-12396245-B2
Application number	US-202117542802-A
Country	US
Kind code	B2
Filing date	Dec 6, 2021
Priority date	Nov 30, 2018
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

A method for fabricating a semiconductor arrangement includes performing a first etching of a semiconductive structure to expose a first portion of a sidewall of a first layer adjacent the semiconductive structure. The first etching forms a first protective layer on the first portion of the sidewall of the first layer, and the first protective layer is formed from a first accumulation of by-product material formed from an etchant of the first etching interacting with the semiconductive structure. The method includes performing a first flash to remove at least some of the first protective layer.

First claim

What is claimed is:

1. A method for fabricating a semiconductor arrangement, comprising:
forming an opening in a dielectric layer, the opening exposing a fin concealed by the dielectric layer;
removing a first portion of the fin exposed though the opening;
forming a first protective layer along a sidewall of the dielectric layer defining the opening concurrently with removing the first portion of the fin;
removing a second portion of the fin exposed though the opening after forming the first protective layer; and
forming a second protective layer along the sidewall of the dielectric layer concurrently with removing the second portion of the fin.

2. The method of claim 1 , wherein:
removing the first portion of the fin comprises removing the first portion of the fin using a first etchant, and
forming the first protective layer comprises forming the first protective layer from a first accumulation of by-product material formed from the first etchant interacting with the fin.

3. The method of claim 2 , wherein:
the first etchant comprises SiCl 4 and O 2 , and
the first protective layer comprises SiO 2 .

4. The method of claim 2 , wherein the first etchant comprises SiF 4 and O 2 .

5. The method of claim 1 , wherein:
the fin comprises a silicon nitride layer, a silicon layer below the silicon nitride layer, and a silicon carbide nitrogen layer below the silicon layer, and
removing the first portion of the fin comprises removing at least a portion of the silicon nitride layer.

6. The method of claim 1 , comprising performing a first flash to remove at least some of the first protective layer.

7. The method of claim 6 , wherein performing the first flash comprises performing the first flash using plasma.

8. The method of claim 6 , wherein performing the first flash comprises performing the first flash prior to removing the second portion of the fin.

9. The method of claim 1 , wherein the first protective layer to comprises at least one of SiO x F y or SiO x Cl y , where x is a positive integer and y is a positive integer.

10. A method for fabricating a semiconductor arrangement, comprising:
forming an opening in a dielectric layer, the opening exposing a fin concealed by the dielectric layer;
removing a first portion of the fin exposed though the opening;
forming a first protective layer along a sidewall of the dielectric layer defining the opening concurrently with removing the first portion of the fin;
removing a second portion of the fin exposed though the opening after forming the first protective layer;
forming a second protective layer along the sidewall of the dielectric layer concurrently with removing the second portion of the fin; and
removing at least a portion of the second protective layer.

11. The method of claim 10 , wherein the first protective layer comprises at least one of SiO x F y or SiO x Cl y , where x is a positive integer and y is a positive integer.

12. The method of claim 10 , comprising performing a first flash to remove at least some of the first protective layer.

13. The method of claim 12 , wherein performing the first flash comprises performing the first flash using plasma.

14. The method of claim 10 , wherein removing the first portion of the fin comprises removing the first portion of the fin using a first etchant.

15. The method of claim 14 , wherein forming the first protective layer comprises forming the first protective layer from a first accumulation of by-product material formed from the first etchant interacting with the fin.

16. A method for fabricating a semiconductor arrangement, comprising:
forming an opening in a dielectric layer, the opening having a first depth and exposing a fin concealed by the dielectric layer;
removing a first portion of the fin exposed though the opening using a first etchant, wherein removing the first portion of the fin deepens the opening to a second depth greater than the first depth;
forming a first protective layer along a sidewall of the dielectric layer defining the opening concurrently with removing the first portion of the fin, wherein the first protective layer is formed from a first accumulation of by-product material formed from the first etchant interacting with the fin;
removing a second portion of the fin exposed though the opening after forming the first protective layer, wherein removing the second portion of the fin deepens the opening to a third depth greater than the second depth; and
forming a second protective layer along the sidewall of the dielectric layer concurrently with removing the second portion of the fin.

17. The method of claim 16 , wherein the first protective layer comprises at least one of SiO x F y or SiO x Cl y , where x is a positive integer and y is a positive integer.

18. The method of claim 16 , wherein the first etchant comprises SiF 4 and O 2 .

19. The method of claim 16 , comprising performing a first flash to remove at least some of the first protective layer.

20. The method of claim 19 , wherein performing the first flash comprises performing the first flash using plasma.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Wei-Lun
• Huang Chao-Hsien
• Lin Li-Te
• Lin Pinyen

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/642 Primary

  Chemical etching · CPC title