Method of forming fine pattern of semiconductor device

Patent metadata

Field	Value
Publication number	US-2016293445-A1
Application number	US-201615066492-A
Country	US
Kind code	A1
Filing date	Mar 10, 2016
Priority date	Apr 2, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

A method of fabricating a semiconductor device is disclosed. The method may include forming an target layer on a substrate, forming a mask pattern on a target layer, performing a first process to etch the target layer and form a first sub-trench, and performing a second process to further etch the target layer and form a second sub-trench. First and second sidewall patterns may be formed on a sidewall of the mask pattern to be used as an etch mask in the first and second processes, respectively. Outer sidewalls of the first and second sidewall patterns may be formed to have different angles with respect to a top surface of the substrate.

First claim

What is claimed is:

1 . A method of fabricating a semiconductor device, the method comprising:
forming an etch target layer on a substrate; forming a mask pattern on the etch target layer; performing a first etch process to etch the etch target layer and form a first sub-trench, the mask pattern and a first sidewall pattern formed on a sidewall of the mask pattern being used as a first etch mask in the first etch process; and performing a second etch process to further etch the etch target layer under the first sub-trench and form a second sub-trench, the mask pattern and a second sidewall pattern formed on the sidewall of the mask pattern being used as a second etch mask in the second etch process, wherein an outer sidewall of the first sidewall pattern has a first angle with respect to a top surface of the substrate, and an outer sidewall of the second sidewall pattern has a second angle different from the first angle with respect to the top surface of the substrate.

2 . The method of claim 1 , wherein the first angle is smaller than the second angle.

3 . The method of claim 1 , wherein the first sidewall pattern is formed to conformally cover a top surface and a side surface of the mask pattern,
the first sidewall pattern is formed in such a way that the outer sidewall of the first sidewall pattern is substantially perpendicular to the top surface of the substrate, and the second sidewall pattern is formed in such a way that the outer sidewall of the second sidewall pattern is slanted at an angle to the top surface of the substrate.

4 . The method of claim 1 , wherein the first and second etch processes are performed using first and second etch gases, respectively,
the first sidewall pattern is a by-product layer that is formed as a result of a chemical reaction between a carbon ion of the first etch gas and a by-product of the etch target layer, and the second sidewall pattern is a by-product layer that is formed as a result of a chemical reaction between a carbon ion of the second etch gas and a by-product of the etch target layer.

5 . The method of claim 1 , wherein the second etch process is performed to change an angle of the outer sidewall of the first sidewall pattern from the first angle to the second angle to form the second sidewall pattern.

6 . The method of claim 1 , wherein the first and second etch processes are performed using first and second etch gases, respectively,
the first etch gas is at least one of C x F y -based gases, where a ratio of y to x ranges from 0 to 2, and CH x F y -based gases, and the second etch gas is at least one of C x F y -based gases, where a ratio of y to x ranges from 2 to 4.

7 . The method of claim 6 , wherein the first etch gas is at least one of C 4 F 6 , CHF 3 , and CH 2 F 2 , and the second etch gas is at least one of C 4 F 8 , CF 4 , and CF 3 .

8 . The method of claim 1 , wherein the second sidewall pattern is formed by providing an O 2 plasma or a NF 3 plasma to the first sidewall pattern.

9 . The method of claim 1 , wherein an inert gas is provided during the second etch process, not during the first etch process.

10 . The method of claim 1 , wherein the first and second etch processes are performed using first and second etch gases, respectively, and
the first etch process is performed in such a way that the first etch gas has an electron temperature lower than an electron temperature of the second etch gas in the second etch process.

11 . The method of claim 10 , wherein a xenon gas is provided during the first etch process, not during the second etch process.

12 . The method of claim 10 , wherein the first etch process is performed with a plasma source power, which is lower than that in the second etch process.

13 . The method of claim 1 , wherein the first and second etch processes are performed using first and second etch gases, respectively,
the first sidewall pattern is formed to allow for the first etch gas to be injected to the etch target layer at the first angle, and the second sidewall pattern is formed to allow for the second etch gas to be injected to the etch target layer at the second angle.

14 . The method of claim 1 , wherein a largest horizontal width of the first sidewall pattern is larger than that of the second sidewall pattern.

15 . The method of claim 1 , wherein a unit etch cycle comprises the first and second etch processes, and the method further comprises repeating the unit etch cycle at least one time.

16 . A method of fabricating a semiconductor device, the method comprising:
forming a mask structure on a substrate, the substrate provided with an etch target layer; performing a first etch process using the mask structure as a first etch mask to etch the etch target layer and form a first trench; and performing a second process using the mask structure as a second etch mask to further etch the etch target layer that is exposed by the first trench and form a second trench, wherein the first etch process is performed using a first etch gas containing at least one of C x F y -based gases, where a ratio of y to x ranges from 0 to 2, and CH x F y -based gases, and the second etch process is performed using a second etch gas containing at least one of C x F y -based gases, where a ratio of y to x ranges from 2 to 4.

17 . The method of claim 16 , wherein the mask structure used as the first etch mask in the first etch process comprises a first sidewall pattern, the first sidewall pattern formed on at least a sidewall of the mask pattern during the first etch process,
the mask structure used as the second etch mask in the second etch process comprises a second sidewall pattern formed on at least the sidewall of the mask pattern, the second sidewall pattern formed by deforming the first sidewall pattern during the second etch process, and the second sidewall pattern is formed in such a way that an outer sidewall of the second sidewall pattern has a greater angle with respect to a top surface of the substrate than an outer sidewall of the first sidewall pattern.

18 . The method of claim 16 , wherein the first etch gas is at least one of C 4 F 6 , CHF 3 , and CH 2 F 2 , and the second etch gas is at least one of C 4 F 8 , CF 4 , and CF 3 .

19 . A method of fabricating a semiconductor device, the method comprising:
forming a mask pattern on a substrate, the substrate provided with an etch target layer; performing a first etch process to etch the etch target layer and form a first sub-trench, the mask pattern and a first sidewall pattern formed on top and side surfaces of the mask pattern being used as a first etch mask in the first etch process; and performing a second etch process to further etch the etch target layer and form a second sub-trench, the mask pattern and a second sidewall pattern formed on the side surface of the mask pattern being used as a second etch mask in the second etch process, wherein an outer sidewall of the first sidewall pattern has a first angle with respect to a top surface of the substrate, an outer sidewall of the second sidewall pattern has a second angle with respect to the top surface of the substrate, and the first angle is greater than the second angle.

20 . A method of claim 19 , wherein the first and second etch processes are performed using first and second etch gases, respectively, and
the first etch process is performed in such a way that the first etch gas has an electron temperature lower than an electron temperature of the second etc

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Je-Woo
• Yoon Junho
• KIM Kyohyeok
• Kim Dongchan
• KIM Sungyeon
• Park Jaehong
• Park Jinyoung
• Jeon Kyungyub

Classifications

• H10P50/283

  by chemical means · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H01L21/31116

  Electricity · mapped topic

• H01L21/31144 Primary

  Electricity · mapped topic