Process of manufacturing Fin-FET device

Patent metadata

Field	Value
Publication number	US-9704974-B2
Application number	US-201514688885-A
Country	US
Kind code	B2
Filing date	Apr 16, 2015
Priority date	Apr 16, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A process of manufacturing a Fin-FET device, and the process includes following steps. An active fin structure and a dummy fin structure are formed from a substrate, and an isolation layer is covered over the active fin structure and the dummy fin structure. Then, the isolation layer above the dummy fin structure is removed, and the dummy fin structure is selectively etched, which a selective ratio of the dummy fin structure to the isolation layer is over 8.

First claim

What is claimed is:

1. A process of manufacturing a Fin-FET device, comprising:
forming an active fin structure and a dummy fin structure from a substrate;
disposing an isolation layer to cover the active fin structure and the dummy fin structure;
selectively removing the isolation layer above the dummy fin structure to expose the dummy fin structure;
selectively etching a first portions of the dummy fin structure to form recesses in the isolation layer, wherein a selective ratio of the dummy fin structure to the isolation layer is over 8;
forming an isolation material in the recesses of the isolation layer; and
recessing the isolation layer and the isolation material.

2. The process of claim 1 , wherein forming the active fin structure and the dummy fin structure from the substrate comprises:
forming a plurality of sidewall spacers on the substrate; and
recessing a top surface of the substrate through the sidewall spacers.

3. The process of claim 1 , further comprising planarizing the isolation layer.

4. The process of claim 1 , wherein the dummy fin structure is selectively etched by a wet etching process using a solution of TMAH, NH 3 or combination thereof.

5. The process of claim 1 , wherein the dummy fin structure is selectively etched by a dry etching process using plasma of HBr, Cl 2 , O 2 , N 2 or combination thereof.

6. The process of claim 1 , wherein the selective ratio is in a range from about 8 to about 15.

7. The process of claim 6 , wherein the selective ratio is in a range from about 10 to about 13.

8. A process of manufacturing a Fin-FET device, comprising:
forming a hardmask layer on a substrate;
forming a plurality of sidewall spacers on the hardmask layer;
etching the hardmask layer and recessing the substrate through the sidewall spacers to form an active fin structure with a first hardmask thereon and a dummy fin structure corresponding to a second hardmask thereon;
disposing an isolation layer to cover the first hardmask and the second hardmask;
removing the isolation layer over the dummy fin structure;
removing the second hardmask;
selectively etching the isolation layer and a first portion of the dummy fin structure, wherein a removing speed of the dummy fin structure is over 8 times higher than a removing speed of the isolation layer;
forming an isolation material on a second portion of the dummy fin structure and in contact with the isolation layer; and
recessing the isolation layer and the isolation material.

9. The process of claim 8 , wherein forming a plurality of sidewall spacers on the hardmask layer comprises:
forming a first dummy pattern on the hardmask layer;
covering a first spacer layer over a top surface and sidewalls of the first dummy pattern;
removing the first spacer layer, wherein the first spacer layer on the sidewalls of the first dummy pattern is remained; and
removing the first dummy pattern.

10. The process of claim 8 , wherein forming a plurality of sidewall spacers on the hardmask layer comprises:
forming a first dummy pattern on the hardmask layer;
covering a first spacer layer over a top surface and sidewalls of the first dummy pattern;
removing a first portion of the first spacer layer, wherein a second portion of the first spacer layer that is on the sidewalls of the first dummy pattern remains;
removing the first dummy pattern to form a second dummy pattern;
covering a second spacer layer over the second dummy pattern;
removing a first portion of the second spacer layer, wherein a second portion of the second spacer layer that is on the sidewalls of the second dummy pattern remains; and
removing the second dummy pattern.

11. The process of claim 8 , further comprising planarizing a top surface of the isolation layer after covering the isolation layer over the first hardmask and the second hardmask.

12. The process of claim 9 , further comprising forming a gate on the active fin structure and overlapped with sidewalls of the active fin structure.

13. The process of claim 8 , wherein the second hardmask is removed by H 3 PO 4 .

14. The process of claim 8 , wherein the isolation layer is recessed by HF.

15. A process of controlling heights of fin structures, the process comprising:
forming a first fin structure that has a plurality of first fins and a second fin structure that has a plurality of second fins from a substrate;
disposing an isolation layer to cover the first fin structure and the second fin structure;
removing the isolation layer above the first fin structure to expose the first fins;
controlling a first selective ratio of the first fin structure to the isolation layer to reduce a height of the first fin structure and form recesses in the isolation layer and respectively on the recessed first fins;
refilling the recesses of the isolation layer with an isolation material;
removing the isolation layer above the second fin structure to expose the second fins;
controlling a second selective ratio of the second fin structure to the isolation layer to reduce a height of the second fin structure, wherein the first fin structure and the second fin structure include different heights; and
recessing the isolation layer and the isolation material.

16. The process of claim 15 , wherein the first selective ratio and the second selective ratio are over 8.

17. The process of claim 16 , wherein the first selective ratio and the second selective ratio are in a range from about 8 to about 15.

18. The process of claim 15 , wherein an amount of reduction of the height of the first fin structure is larger than an amount of reduction of the height of the second fin structure such that the height of the first fin structure is lower than the height of the second fin structure.

19. The process of claim 15 , wherein an amount of reduction of the height of the first fin structure is smaller than an amount of reduction of the height of the second fin structure such that the height of the first fin structure is higher than the height of the second fin structure.

20. The process of claim 1 , wherein the isolation material is made of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Chia-Wei
• Chang An-Shen
• Liu Eric Chih-Fang
• Chen Ryan Chia-Jen
• LIN Chia-Tai
• Peng Chih-Tang

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H01L21/3086

  Electricity · mapped topic

• H01L29/66795 Primary

  Electricity · mapped topic