Fin field effect transistor and semiconductor device

Patent metadata

Field	Value
Publication number	US-9685554-B1
Application number	US-201615062215-A
Country	US
Kind code	B1
Filing date	Mar 7, 2016
Priority date	Mar 7, 2016
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first ridge portion embedded in the first concave and the drain includes a second ridge portion embedded in the second concave, wherein the first and second ridge portions extend along a height direction of the semiconductor fin.

First claim

What is claimed is:

1. A fin field effect transistor (FinFET), comprising:
a gate stack;
a semiconductor fin embedded in the gate stack, the semiconductor fin extending along a widthwise direction of the gate stack and having a first concave and a second concave exposed at sidewalls of the gate stack respectively; and
a source and a drain disposed at two opposite sides of the gate stack, the source comprising a first ridge portion filled in the first concave and embedded in the gate stack, and the drain comprising a second ridge portion filled in the first concave and embedded in the gate stack, wherein the first and second ridge portions extend along a height direction of the semiconductor fin.

2. The FinFET of claim 1 , wherein the gate stack comprises:
a gate;
a gate dielectric layer; and
a pair of spacers disposed on sidewalls of the gate, the semiconductor fin being embedded in the gate and the pair of spacers, the gate dielectric layer being between the semiconductor fin and the pair of spacers and being between the semiconductor fin and the gate.

3. The FinFET of claim 2 , wherein the first concave of the semiconductor fin and the gate dielectric layer provide a first V-groove for accommodating the first ridge portion, and the second concave of the semiconductor fin and the gate dielectric layer provide a second V-groove for accommodating the second ridge portion.

4. The FinFET of claim 1 , wherein the first ridge portion comprises two first main surfaces interconnected at a first ridge line of the first ridge portion, the second ridge portion comprises two second main surfaces interconnected at a second ridge line of the second ridge portion, the first main surfaces are connected to the first concave of the semiconductor fin and the second main surfaces are connected to the second concave of the semiconductor fin.

5. The FinFET of claim 4 , wherein the first and second ridge lines extend along a height direction of the semiconductor fin.

6. The FinFET of claim 4 , wherein the first and second ridge lines are in contact with the semiconductor fin.

7. The FinFET of claim 4 , wherein included angles between the first main surfaces and between the second main surfaces are smaller than 90 degrees.

8. A fin field effect transistor (FinFET), comprising:
a gate stack;
a semiconductor fin embedded in the gate stack, the semiconductor fin extending along a widthwise direction of the gate stack and having a first V-shaped concave and a second V-shaped concave exposed at sidewalls of the gate stack respectively; and
a source and a drain disposed at two opposite sides of the gate stack, the source comprising a first main portion and a first ridge portion protruding from the first main portion, the drain comprising a second main portion and a second ridge portion protruding from the second main portion, the first and second ridge portions being embedded in the first V-shaped concave and the second V-shaped concave respectively, wherein the first and second ridge portions extend along a height direction of the semiconductor fin.

9. The FinFET of claim 8 , wherein the first and second main portions are distributed outside the first and second V-shaped concaves.

10. The FinFET of claim 8 , wherein the first ridge portion comprises two first main surfaces interconnected at a first ridge line of the first ridge portion, the second ridge portion comprises two second main surfaces interconnected at a second ridge line of the second ridge portion, the first main surfaces are connected to the first V-shaped concave of the semiconductor fin and the second main surfaces are connected to the second V-shaped concave of the semiconductor fin.

11. The FinFET of claim 10 , wherein the first and second ridge lines extend along a height direction of the semiconductor fin.

12. The FinFET of claim 10 , wherein the first and second ridge lines are in contact with the semiconductor fin.

13. The FinFET of claim 10 , wherein included angles between the first main surfaces and between the second main surfaces are smaller than 90 degrees.

14. A semiconductor device, comprising:
a first fin field effect transistor (FinFET) comprising:
a first gate stack;
a first semiconductor fin embedded in the first gate stack, the first semiconductor fin extending along a widthwise direction of the first gate stack and having a first concave and a second concave exposed at sidewalls of the gate stack respectively;
a first source and a first drain disposed at two opposite sides of the first gate stack, the first source comprising a first ridge portion embedded in the first concave and the first drain comprising a second ridge portion embedded in the second concave and the first and second ridge portions extending along a height direction of the first semiconductor fin;

a second FinFET, comprising:
a second gate stack;
a second semiconductor fin embedded in the second gate stack, the second semiconductor fin extending along a widthwise direction of the second gate stack and having a third concave and a fourth concave exposed at sidewalls of the second gate stack respectively; and
a second source and a second drain disposed at two opposite sides of the second gate stack, the second source comprising a first rounding protrusion embedded in the third concave and the second drain comprising a second rounding protrusion embedded in the fourth concave, the first and second rounding protrusions extending along a height direction of the second semiconductor fin.

15. The semiconductor device of claim 14 , wherein the first ridge portion comprises two first main surfaces interconnected at a first ridge line of the first ridge portion, the second ridge portion comprises two second main surfaces interconnected at a second ridge line of the second ridge portion, the first main surfaces are connected to the first concave of the semiconductor fin and the second main surfaces are connected to the second concave of the semiconductor fin.

16. The semiconductor device of claim 15 , wherein the first and second ridge lines extend along a height direction of the semiconductor fin.

17. The semiconductor device of claim 15 , wherein the first and second ridge lines are in contact with the semiconductor fin.

18. The semiconductor device of claim 15 , wherein included angles between the first main surfaces and between the second main surfaces are smaller than 90 degrees.

19. The semiconductor device of claim 14 , wherein depths of the first and second concaves are greater than depths of the third and fourth concaves.

20. The semiconductor device of claim 14 , wherein profiles of the first and second ridge portions are sharper than profiles of the first and second rounding protrusions.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Che-Cheng
• Lin Chih-Han
• Tseng Horng-Huei

Classifications

• H01L27/0886

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L29/7853 Primary

  Electricity · mapped topic

• H01L29/0657

  Electricity · mapped topic

• H10D84/853

  comprising FinFETs · CPC title