Single event upset-tolerant latch circuit and flip-flop circuit

Patent metadata

Field	Value
Publication number	US-2021194470-A1
Application number	US-201816621691-A
Country	US
Kind code	A1
Filing date	May 16, 2018
Priority date	Jun 12, 2017
Publication date	Jun 24, 2021
Grant date	—

Abstract

Provided are a latch circuit and a flip-flop circuit each having more excellent tolerance to single event upset (SEU). The single event upset (SEU)-tolerant latch circuit of the present invention is configured such that three transistors for redundancy are added to each of eight transistors constituting a conventional DICE latch circuit, at respective positions consisting of a serial position, a parallel position and a parallel-serial position so as to form a four-transistor circuit in which a serially duplicated circuit is duplicated in parallel, and each of a first data input part and a second data input part is also made dually redundant.

First claim

1 . A single event upset-tolerant latch circuit configured such that four Dual Interlocked Storage Cell (DICE) elements are connected in series and in a loop configuration, each of the DICE elements being comprised of a p-type transistor and an n-type transistor, wherein a gate terminal in each one of the p-type and n-type transistors and a drain terminal in the other are mutually connected, each of the DICE elements having a first node interconnecting between the gate terminal of the p-type transistor and the drain terminal of the n-type transistor, arid a second node interconnecting between the drain terminal of the p-type transistor and the gate terminal of the n-type transistor, the single event upset-tolerant latch circuit comprising:
a first DICE element comprised of a first p-type transistor (P 1 _ 1 ) and a first n-type transistor (N 1 _ 1 ), wherein a gate terminal in each one of the first p-type and n-type transistors and a drain terminal in the other are mutually connected; a second DICE element comprised of a second p-type transistor (P 2 _ 1 ) and a second n-type transistor (N 2 _ 1 ), wherein a gate terminal in each one of the second p-type and n-type transistors and a drain terminal in the other are mutually connected; a third DICE element comprised of a third p-type transistor (P 3 _ 1 ) and a third n-type transistor (N 3 _ 1 ), wherein a gate terminal in each one of the third p-type and n-type transistors and a drain terminal in the other are mutually connected; and a fourth DICE element comprised of a fourth p-type transistor (P 4 _ 1 ) and a fourth n-type transistor (N 4 _ 1 ), wherein a gate terminal in each one of the fourth p-type and n-type transistors and a drain terminal in the other are mutually connected; wherein: a node interconnecting between a gate terminal of a p-type transistor comprised in the first DICE element and a drain terminal of an n-type transistor comprised in the first DICE element forms a first DICE element's first node; a node interconnecting between a gate terminal of a p-type transistor comprised in the second DICE element and a drain terminal of an n-type transistor comprised in the second DICE element forms a second DICE element's first node; a node interconnecting between a gate terminal of a p-type transistor comprised in the third DICE element and a drain terminal of an n-type transistor comprised in the third DICE element forms a third DICE element's first node; a node interconnecting between a gate terminal of a p-type transistor comprised in the fourth DICE element and a drain terminal of an n-type transistor comprised in the fourth DICE element forms a fourth DICE element's first node; a node interconnecting between a drain terminal of a p-type transistor comprised in the first DICE element and a gate terminal of an n-type transistor comprised in the first DICE element forms a first DICE element's second node; a node interconnecting between a drain terminal of a p-type transistor comprised in the second DICE element and a gate terminal of an n-type transistor comprised in the second DICE element forms a second DICE element's second node; a node interconnecting between a drain terminal of a p-type transistor comprised in the third DICE element and a gate terminal of an n-type transistor comprised in the third DICE element forms a third DICE element's second node; and a node interconnecting between a drain terminal of a p-type transistor comprised in the fourth DICE element and a gate terminal of an n-type transistor comprised in the fourth DICE element forms a fourth DICE element's second node; and wherein: the first DICE element's first node is connected to the fourth DICE element's second node; the second DICE element's first node is connected to the first DICE element's second node; the third DICE element's first node is connected to the second DICE element's second node; and the fourth DICE element's first node is connected to the third DICE element's second node; and wherein: the second DICE element's first node and the fourth DICE element's first node are connected, respectively, to a first data input part and a second data input part each configured such that a conduction state thereof is controlled by control of a clock; and at least one of the first DICE element's second node, the second DICE element's second node, the third DICE element's second node and the fourth DICE element's second node is connected to a data output part; and wherein: each of the first p-type transistor (P 1 _ 1 ), the first n-type transistor (N 1 _ 1 ), the second p-type transistor (P 2 _ 1 ), the second n-type transistor (N 2 _ 1 ), the third p-type transistor (P 3 _ 1 ), the third n-type transistor (N 3 _ 1 ), the fourth p-type transistor (P 4 _ 1 ) and the fourth n-type transistor (N 4 _ 1 ) is configured such that three transistors for redundancy are added thereto at respective positions consisting of a serial position, a parallel position and a parallel-serial position so as to form a four-transistor circuit in which a serially duplicated circuit is duplicated in parallel; and each of the first data input part and the second data input part is made dually redundant.

2 . The single event upset-tolerant latch circuit as recited in claim 1 , wherein each of the redundant first, second, third and fourth DICE elements is configured such that a connection with a positive power supply or a negative power supply is controlled by control of a clock having a phase reverse to that of the clock for controlling the first and second data input parts.

3 . The single event upset-tolerant latch circuit as recited in claim 2 , wherein,
the transistor subject to redundancy and the parallel-duplicating transistor are configured such that gate terminals thereof are connected to a common line; the serially-duplicating transistor and the parallel-serially-duplicating transistor are configured such that gate terminals thereof are connected to a common line; the transistor subject to redundancy and the serially-duplicating transistor are connected in series; and the parallel-duplicating transistor and the parallel-serially-duplicating transistor are connected in series.

4 . The single event upset-tolerant latch circuit as recited in claim 3 , wherein the serial, parallel and parallel-serial duplications are implemented by:
connecting first to fourth serially-duplicating p-type transistors (P 1 _ 2 , P 2 _ 2 , P 3 _ 2 , P 4 _ 2 ) in series, respectively, to negative power supply (V SS ) sides of the first to fourth p-type transistors (P 1 _ 1 , P 2 _ 1 , P 3 _ 1 , P 4 _ 1 ) each constituting a respective one of the first to fourth DICE elements, and connecting four serially-duplicating n-type transistors (N 1 _ 2 , N 2 _ 2 , N 3 _ 2 , N 4 _ 2 ) in series, respectively, to positive power supply (V DD ) sides of the four n-type transistors (N 1 _ 1 , N 2 _ 1 , N 3 _ 1 , N 4 _ 1 ) each constituting a respective one of the redundant first to fourth DICE elements; connecting first to fourth parallel-duplicating p-type transistors (P 1 _ 3 , P 2 _ 3 , P 3 _ 3 , P 4 _ 3 ) whose gate terminals are connected, respectively, to gate terminals of the first to fourth p-type transistors (P 1 _ 1 , P 2 _ 1 , P 3 _ 1 , P 4 _ 1 ) each constituting a respective one of the redundant first to fourth DICE elements, and first to fourth parallel-serially-duplicating p-type transistors (P 1 _ 4 , P 2 _ 4 , P 3 _ 4 , P 4 _ 4 ) whose gate terminals are connected, respectively, to gate terminals of the first to fourth serially-duplicating p-type transistors (P 1 _ 2 , P 2 _ 2 , P 3 _ 2 , P 4 _ 2 ) each constituting a respective one of the redundant first to fourth DICE elements, in series, said serially connected p-type transistors (P 1 _ 3 -P 1 _ 4 , P 2 _ 3 -P 2 _ 4 , P 3 _ 3 -P 3 _ 4 , P 4 _ 3 -P 4 _ 4 ) respectively being place

Assignees

• Japan Aerospace Exploration
• High Reliability Eng & Components Corporation

Inventors

• Maru Akifumi
• Kuboyama Satoshi
• Ebihara Tsukasa
• Makihara Akiko

Classifications

• H03K3/356078

  with synchronous operation · CPC title

• H03K3/0375 Primary

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title

• H03K3/0372

  of the primary-secondary type · CPC title