ZQ calibration circuit for multiple interfaces

Patent metadata

Field	Value
Publication number	US-12394452-B2
Application number	US-202318464618-A
Country	US
Kind code	B2
Filing date	Sep 11, 2023
Priority date	Sep 19, 2022
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

A ZQ calibration circuit includes: a ZQ controller configured to detect an end of one interface mode, among a plurality of interface modes in which ZQ calibration is supported, and to instruct a switch to another interface mode in response to the one interface mode coming to an end; a ZQ engine configured to generate a first reference voltage corresponding to the one interface mode through a multi-reference voltage generator, to generate a second reference voltage corresponding to the another interface mode in response to the switch to the another interface mode being instructed, to perform the ZQ calibration based on the first reference voltage or the second reference voltage, and to output a calibration code; and a ZQ driver configured to output an output signal through an input/output pad based on the calibration code.

First claim

What is claimed is:

1. A ZQ calibration circuit comprising:
a ZQ controller configured to detect an end of one interface mode from among a plurality of interface modes in which ZQ calibration is supported, and to instruct a switch to another interface mode in response to the one interface mode coming to an end;
a ZQ engine configured to generate a first reference voltage corresponding to the one interface mode through a multi-reference voltage generator, to generate a second reference voltage corresponding to the another interface mode in response to the switch to the another interface mode being instructed, to perform the ZQ calibration based on the first reference voltage or the second reference voltage, and to output a calibration code; and
a ZQ driver configured to output an output signal through an input/output pad based on the calibration code.

2. The ZQ calibration circuit of claim 1 , wherein
the ZQ engine is configured to perform the ZQ calibration for the plurality of interface modes during a single unit of ZQ time.

3. The ZQ calibration circuit of claim 1 , wherein
the plurality of interface modes comprise a first interface mode in which a common level of swing of the output signal corresponds to half of an input/output voltage, and a second interface mode in which a minimum point of the swing of the output signal corresponds to a ground voltage.

4. The ZQ calibration circuit of claim 1 , wherein
the ZQ engine is configured to generate a flag signal in response to the one interface mode coming to an end, and
the ZQ controller is configured to detect that the one interface mode comes to an end, in response to receiving the flag signal.

5. The ZQ calibration circuit of claim 1 , wherein
the ZQ engine further comprises:
a comparator connected to a ZQ pad and configured to receive at least one of the first reference voltage or the second reference voltage from the multi-reference voltage generator, to compare the first reference voltage or the second reference voltage with a voltage of the ZQ pad, and to output a result of the comparison; and
a counter configured to output the calibration code based on the result of the comparison.

6. The ZQ calibration circuit of claim 5 , wherein
the counter is configured to generate a flag signal in response to the one interface mode or the another interface mode coming to an end, and to transmit the calibration code at a time of the end to the ZQ controller.

7. The ZQ calibration circuit of claim 1 , wherein
the ZQ controller comprises:
a mode end detector configured to detect the end of the one interface mode and to output a mode end signal;
a mode switcher configured to output a mode switch signal to the ZQ engine when receiving the mode end signal; and
a register configured to store the mode end signal and the calibration code.

8. The ZQ calibration circuit of claim 7 , wherein
the mode end detector is configured to output the mode end signal in response to the output signal swings within a specific range with respect to the first reference voltage or the second reference voltage.

9. The ZQ calibration circuit of claim 7 , wherein
the register is configured to store the calibration code corresponding to a time point at which the mode end signal is output.

10. The ZQ calibration circuit of claim 9 , wherein
the register is configured to store the calibration code corresponding to a time point at which a ZQ enable signal for the ZQ calibration is terminated.

11. The ZQ calibration circuit of claim 7 , wherein
the mode switcher is configured to generate a reset signal for resetting at least a portion of an operation of the ZQ controller and an operation of the ZQ engine in response to receiving the mode end signal.

12. The ZQ calibration circuit of claim 11 , wherein
the at least a portion of the ZQ controller and the operation of the ZQ engine are configured to reset based on the reset signal, in a state in which a ZQ enable signal for the ZQ calibration is maintained.

13. A ZQ calibration method of a ZQ calibration circuit, the ZQ calibration method comprising:
performing ZQ calibration based on a first reference voltage in one interface mode from among a plurality of interface modes in which the ZQ calibration is supported;
detecting an end of the one interface mode;
instructing a switch to another interface mode in response to the one interface mode coming to an end;
generating a second reference voltage corresponding to the another interface mode in response to the switch to the another interface mode being instructed;
performing the ZQ calibration based on the second reference voltage and outputting a calibration code; and
outputting an output signal through an input/output pad based on the calibration code.

14. The ZQ calibration method of claim 13 , further comprising:
receiving a ZQ command indicating the ZQ calibration,
wherein
the ZQ calibration for the one interface mode and the ZQ calibration for the another interface mode are performed together during a ZQ time based on the ZQ command.

15. The ZQ calibration method of claim 13 , wherein
the one interface mode is detected to come to an end in response to the output signal swinging within a first range with respect to the first reference voltage.

16. The ZQ calibration method of claim 13 , further comprising:
receiving a flag signal after the ZQ calibration for the one interface mode comes to an end,
wherein
the one interface mode is detected to come to an end in response to the flag signal being received.

17. The ZQ calibration method of claim 13 , further comprising:
generating a first mode end signal in response to the end of the one interface mode being detected; and
storing the calibration code corresponding to a time point at which the first mode end signal is generated.

18. A memory device comprising:
a memory controller;
a buffer chip configured to operate under control of the memory controller; and
a nonvolatile memory connected to the buffer chip,
wherein
the memory controller, the buffer chip, and the nonvolatile memory are configured to operate in a plurality of interface modes in which ZQ calibration is supported, and
the ZQ calibration is configured to be performed based on a first reference voltage in one interface mode, among the plurality of interface modes, and comprises instructing a switch to another interface mode in response to the one interface mode coming to an end, generating a second reference voltage corresponding to the another interface mode in response to the switch to the another interface mode being instructed, performing the ZQ calibration based on the second reference voltage, outputting a calibration code, and outputting an output signal through an input/output pad based on the calibration code.

19. The memory device of claim 18 , wherein
the ZQ calibration is configured to be performed on the plurality of interface modes during a single unit ZQ time.

20. The memory device of claim 18 , wherein
the plurality of interface modes comprise a first interface mode in which a common level of swing of the output signal corresponds to half of an input/output voltage, and a second interface mode in which a minimum point of the swing of the output signal corresponds to a ground voltage.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Tongsung
• Kwak Junghwan
• Bae Seungjun
• Yoon Chiweon
• Chun Byungkwan
• Jo Youngmin

Classifications

• G11C2207/2254

  Calibration · CPC title

• G06F2213/16

  Memory access · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/021

  in voltage or current generators · CPC title