Reduction of ZQ calibration time

Patent metadata

Field	Value
Publication number	US-10891989-B2
Application number	US-201916700250-A
Country	US
Kind code	B2
Filing date	Dec 2, 2019
Priority date	Nov 30, 2018
Publication date	Jan 12, 2021
Grant date	Jan 12, 2021

Abstract

A memory system includes an external calibration device that has a predetermined impedance and a first memory device with a first pad for selective connection to the external calibration device. The first memory device also includes an internal calibration device having an impedance that is programmable and a second pad connected to the internal calibration device. The system further includes a second memory device having a third pad for selective connection to the second pad of the first memory device. A processing device is operatively coupled to the first memory device and the second memory device. The processing device programs the impedance of the internal calibration device of the first memory device based on the external calibration device, and programs an impedance of a termination component in the second memory device based on the impedance of the internal calibration device of the first memory device.

First claim

We claim:

1. An apparatus, comprising:
a ZQ resistor;
a first semiconductor device, including:
a first pull-up circuit, and
a first pull-down circuit, wherein one of the first pull-up circuit or the first pull-down circuit is configured to connect to the ZQ resistor; and

a second semiconductor device, the second semiconductor device including:
a second pull-up circuit, and
a second pull-down circuit, wherein one of the second pull-up circuit or the second pull-down circuit is configured to connect to the other of the first pull-up circuit or the first pull-down circuit,

wherein the one of the second pull-up circuit or the second pull-down circuit does not access the ZQ resistor.

2. The apparatus of claim 1 , further comprising:
a third semiconductor device, including:
a third pull-up unit, and
a third pull-down unit, wherein one of the third pull-up circuit or the third pull-down circuit is configured to connect to the other of the first pull-up circuit or the first pull-down circuit, the one of the third pull-up circuit or the third pull-down circuit corresponds to the one of the second pull-up circuit or the second pull-down circuit.

3. The apparatus of claim 2 , wherein the second and third semiconductor devices each include an arbiter circuit configured to prevent a concurrent connection of the second semiconductor device and the third semiconductor device to the other of the first pull-up circuit or the first pull-down circuit.

4. The apparatus of claim 1 , further comprising:
a third semiconductor device, including:
a third pull-up unit, and
a third pull-down unit, wherein one of the third pull-up circuit or the third pull-down circuit is configured to connect to the ZQ resistor.

5. The apparatus of claim 4 , wherein the first and third semiconductor devices each include an arbiter circuit configured to prevent a concurrent connection of the first semiconductor device and the third semiconductor device to the ZQ resistor.

6. The apparatus of claim 4 , further comprising:
a fourth semiconductor device, the fourth semiconductor device including:
a fourth pull-up circuit, and
a fourth pull-down circuit, wherein one of the fourth pull-up circuit or the fourth pull-down circuit is configured to connect to the other of the third pull-up circuit or the third pull-down circuit.

7. An apparatus, comprising:
a ZQ resistor;
a first semiconductor device, including:
a first pull-up circuit, and
a first pull-down circuit, wherein one of the first pull-up circuit or the first pull-down circuit is configured to connect to the ZQ resistor;

a second semiconductor device, the second semiconductor device including:
a second pull-up circuit, and
a second pull-down circuit, wherein one of the second pull-up circuit or the second pull-down circuit is configured to connect to the other of the first pull-up circuit or the first pull-down circuit;

a third semiconductor device, including:
a third pull-up unit, and
a third pull-down unit, wherein one of the third pull-up circuit or the third pull-down circuit is configured to connect to the ZQ resistor; and

a fourth semiconductor device, the fourth semiconductor device including:
a fourth pull-up circuit, and
a fourth pull-down circuit, wherein one of the fourth pull-up circuit or the fourth pull-down circuit is configured to connect to the other of the third pull-up circuit or the third pull-down circuit,

wherein the one of the fourth pull-up circuit or the fourth pull-down circuit does not access the ZQ resistor.

8. An apparatus, comprising:
a ZQ resistor;
a first semiconductor device, including:
a first pull-up circuit, and
a first pull-down circuit, wherein one of the first pull-up circuit or the first pull-down circuit is configured to connect to the ZQ resistor; and

a second semiconductor device, the second semiconductor device including:
a second pull-up circuit, and
a second pull-down circuit, wherein one of the second pull-up circuit or the second pull-down circuit is configured to connect to the other of the first pull-up circuit or the first pull-down circuit,

wherein the first semiconductor device includes a first calibration circuit configured to perform a first calibration on the one of the first pull-up circuit or the first pull-down circuit with the ZQ resistor and perform a second calibration on the other of the first pull-up circuit or the first pull-down circuit with a calibration result from the first calibration.

9. The apparatus of claim 8 , wherein the second semiconductor device includes a second calibration circuit configured to perform a third calibration on the one of the second pull-up circuit or the second pull-down circuit with a calibration result from the second calibration or the calibration result from the first calibration and perform a fourth calibration on the other of the second pull-up circuit or the second pull-down circuit with a calibration result from the third calibration.

10. An apparatus, comprising:
a ZQ resistor;
a first semiconductor device having a first ZQ calibration circuit including a first input node and a first output node, the first input node configured to connect to the ZQ resistor; and
a second semiconductor device having a second ZQ calibration circuit including a second input node and a second output node, the second input node configured to connect to the first output node.

11. The apparatus of claim 10 , wherein the second ZQ calibration circuit does not access the ZQ resistor.

12. The apparatus of claim 10 , further comprising:
a third semiconductor device having a third ZQ calibration circuit including a third input node and a third output node, the third input node configured to connected to the first output node.

13. The apparatus of claim 12 , wherein the second and third semiconductor devices each include an arbiter circuit configured to prevent a concurrent connection of the second and third ZQ calibration circuits to the first output node.

14. The apparatus of claim 10 , further comprising:
a third semiconductor device having a third ZQ calibration circuit including a third input node and a third output node, the third input node configured to connected to the ZQ resistor.

15. The apparatus of claim 14 , wherein the first and third semiconductor devices each include an arbiter circuit configured to prevent a concurrent connection of the first and third ZQ calibration circuits to the ZQ resistor.

16. The apparatus of claim 14 , further comprising:
a fourth semiconductor device having a fourth ZQ calibration circuit including a fourth input node and a fourth output node, the fourth input node configured to connected to the third output node.

17. The apparatus of claim 16 , wherein the fourth ZQ calibration circuit does not access the ZQ resistor.

18. The apparatus of claim 10 , wherein the first semiconductor device includes a first pull-up circuit and a first pull-down circuit, and
wherein the first ZQ calibration circuit is configured to perform a first calibration on one of the first pull-up circuit or the first pull-down circuit with the ZQ resistor and perform a second calibration on the other of the first pull-up circuit or the first pull-down circuit with a calibration result from the first calibration.

19. The apparatus of claim 18 , wherein the second semiconductor device includes a second pull-up circuit and a second pull-down circuit, and
wherein the second ZQ calibration circuit is configured to perform a third calibration on one of the second p

Assignees

• Micron Technology Inc

Inventors

• Satoh Yasuo
• He Yuan

Classifications

• G11C2207/2254

  Calibration · CPC title

• G11C29/50008 Primary

  of impedance · CPC title

• G11C7/1057 Primary

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1048 Primary

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G06F3/0673

  Single storage device · CPC title