Semiconductor device

Patent metadata

Field	Value
Publication number	US-12388022-B2
Application number	US-202217885025-A
Country	US
Kind code	B2
Filing date	Aug 10, 2022
Priority date	Nov 25, 2021
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

A semiconductor device includes a gate structure including a gate electrode on a substrate. A source/drain pattern is on the substrate and positioned on a side surface of the gate electrode. A source/drain contact is on the source/drain pattern. A first conductive pad is on the source/drain contact. A second conductive pad is on the gate structure. A via plug penetrates the first conductive pad and is connected to the source/drain contact. A gate contact penetrates the second conductive pad and is connected to the gate electrode. A portion of the via plug protrudes from the first conductive pad. A portion of the gate contact protrudes from the second conductive pad. A height from an upper surface of the gate structure to an upper surface of the via plug is equal to a height from the upper surface of the gate structure to an upper surface of the gate contact.

First claim

What is claimed is:

1. A semiconductor device comprising:
a gate structure including a gate electrode on a substrate;
a source/drain pattern disposed on the substrate and positioned on a side surface of the gate electrode;
a source/drain contact disposed on the source/drain pattern and connected to the source/drain pattern;
a first conductive pad on the source/drain contact;
a second conductive pad on the gate structure;
a via plug penetrating the first conductive pad and connected to the source drain contact; and
a gate contact penetrating the second conductive pad and connected to the gate electrode,
wherein a portion of the via plug protrudes from an upper surface of the first conductive pad,
a portion of the gate contact protrudes from an upper surface of the second conductive pad, and
a height from an upper surface of the gate structure to an upper surface of the via plug is equal to a height from the upper surface of the gate structure to an upper surface of the gate contact.

2. The semiconductor device of claim 1 , wherein:
a width of the upper surface of the via plug is less than a width of the via plug disposed on the upper surface of the first conductive pad; and
a width of the upper surface of the gate contact is less than a width of the gate contact disposed on the upper surface of the second conductive pad.

3. The semiconductor device of claim 2 , wherein a width of the source/drain contact increases as a distance from the substrate increases.

4. The semiconductor device of claim 1 , wherein:
the first conductive pad includes a pad through hole; and
the via plug directly contacts side walls of the pad through hole.

5. The semiconductor device of claim 1 , wherein the upper surface of e gate structure is lower than the upper surface of the source/drain contact.

6. The semiconductor device of claim 5 , wherein a height from the upper surface of the gate structure to the upper surface of the second conductive pad is equal to a height from the upper surface of the gate structure to the upper surface of the source/drain contact.

7. The semiconductor device of claim 1 , wherein the upper surface of the gate structure is disposed on a same plane as the upper surface of the source drain contact.

8. The semiconductor device of claim 1 , wherein a thickness of the second conductive pad is greater than or equal to a thickness of the first conductive pad.

9. The semiconductor device of claim 1 , wherein:
the via plug includes a lower via plug and an upper via plug on the lower via plug; and
the lower via plug is directly connected to the source drain contact and disposed in the first conductive pad.

10. The semiconductor device of claim 9 , wherein the lower via plug and the upper via plug each have a single material film structure.

11. The semiconductor device of claim 1 , wherein an entirety of a lower surface of the second conductive pad is disposed on the upper surface of the gate structure.

12. The semiconductor device of claim 1 , wherein the gate contact and the via plug each have a single material structure.

13. A semiconductor device comprising:
a gate structure on a substrate, the gate structure including a gate electrode and a gate capping pattern on the gate electrode;
a source/drain pattern disposed on the substrate and positioned on a side surface of the gate electrode;
a source/drain contact disposed on the source/drain pattern and connected to the source/drain pattern;
a first conductive pad on the source/drain contact;
a second conductive pad on the gate capping pattern;
a via plug penetrating the first conductive pad and connected to the source/drain contact; and
a gate contact penetrating the second conductive pad and the gate capping pattern, and connected to the gate electrode,
wherein a width of the via plug decreases as a distance from an upper surface of the first conductive pad increases, and
a width of the gate contact decreases as a distance from an upper surface of the second conductive pad increases.

14. The semiconductor device of claim 13 , wherein:
the via plug includes a lower via plug and an upper via plug on the lower via plug; and
the lower via plug is directly connected to the source/drain contact and disposed in the first conductive pad.

15. The semiconductor device of claim 14 , wherein:
the first conductive pad includes a pad through hole; and
the lower via plug directly contacts side walls of the pad through hole.

16. The semiconductor device of claim 13 , wherein the gate contact and the via plug each have a single material film structure.

17. The semiconductor device of claim 13 , wherein a thickness of the second conductive pad is greater than or equal to a thickness of the first conductive pad.

18. A semiconductor device comprising:
a multi-channel active pattern on a substrate;
a gate structure that is disposed on the multi-channel active pattern, the gate structure includes a gate electrode and a gate capping pattern, the gate capping pattern is disposed on the gate electrode;
a source/drain pattern disposed on the substrate and positioned on a side surface of the gate electrode;
a source/drain contact disposed on the source/drain pattern and connected to the source/drain pattern;
a first conductive pad on the source/drain contact;
a second conductive pad on the gate capping pattern;
a via plug penetrating the first conductive pad and connected to the source/drain contact; and
a gate contact penetrating the second conductive pad and the gate capping pattern and connected to the gate electrode,
wherein the via plug includes a lower via plug disposed in the first conductive pad and an upper via plug on the lower via plug,
the gate contact includes a lower gate contact disposed in the second conductive pad and an upper gate contact on the lower gate contact,
a width of an upper surface of the upper via plug is less than a width of a lower surface of the via plug disposed on an upper surface of the first conductive pad, and
a width of an upper surface of the upper gate contact is less than a width of a lower surface of the gate contact disposed on an upper surface of the second conductive pad.

19. The semiconductor device of claim 18 , wherein:
the lower via plug includes a same material as the lower gate contact;
the upper via plug includes a same material as the upper gate contact; and
the lower gate contact, the upper gate contact, the lower via plug, and the upper via plug each have a single material film structure.

20. The semiconductor device of claim 18 , wherein a thickness of the second conductive pad is greater than or equal to a thickness of the first conductive pad.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jun Ki
• Hwang Yoon Tae
• Kim Wan Don
• Kim Sung Hwan
• Kim Tae Yeol

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/083 Primary

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title