Semiconductor device and a method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9893062-B2
Application number	US-201615141476-A
Country	US
Kind code	B2
Filing date	Apr 28, 2016
Priority date	Apr 28, 2016
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first side wall spacers is different from a second depth of the first space above the first gate electrode layer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a first gate structure and a second gate structure over a substrate, the first gate structure including a first gate electrode layer and first sidewall spacers disposed on both side faces of the first gate electrode layer, the second gate structure including a second gate electrode layer and second sidewall spacers disposed on both side faces of the second gate electrode layer, a first insulating layer being disposed between the first gate structure and the second gate structure;
recessing the first and second gate electrode layers, and recessing the first and second sidewall spacers, thereby forming a first space over the recessed first gate electrode layer and the recessed first sidewall spacers and a second space over the recessed gate electrode layer and the recessed second sidewall spacers;
conformally forming a first insulating material in direct contact with the recessed first gate electrode layer, the recessed first sidewall spacers, the recessed gate electrode layer and the recessed second sidewall spacers;
forming a second insulating material on the first insulating material, the second insulating material being different from the first insulating material; and
performing a planarization operation, thereby exposing part of the first insulating material, wherein:
after the planarization operation, a first protective layer made of the first insulating material is formed over the recessed first gate electrode, a second protective layer made of the first insulating material is formed over the recessed second gate electrode, a first etch-stop layer is formed on the first protective layer and a second etch-stop layer is formed on the second protective layer, and
a first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.

2. The method of claim 1 , wherein the first depth of the first space above the first sidewall spacers is smaller than the second depth of the first space above the first gate electrode layer.

3. The method of claim 2 , wherein a difference between the first depth and the second depth is in a range from 5 nm to 15 nm.

4. The method of claim 1 , wherein the first and second gate electrode layers are first recessed, and then the first and second sidewall spacers are recessed.

5. The method of claim 1 , wherein:
the first insulating material is an aluminum based insulating material, and
the second insulating material is made of a silicon nitride based insulating material.

6. The method of claim 1 , wherein:
the first protective layer is disposed on the first sidewall spacers and the first gate electrode layer, and
the first etch-stop layer is disposed above the first gate electrode layer.

7. A method of manufacturing a semiconductor device, the method comprising:
forming a first gate structure and a second gate structure over a substrate, the first gate structure including a first gate electrode layer and first sidewall spacers disposed on both side faces of the first gate electrode layer, the second gate structure including a second gate electrode layer and second sidewall spacers disposed on both side faces of the second gate electrode layer, a first source/drain region being disposed in an area between the first gate structure and the second gate structure, and a first insulating layer being disposed over the first source/drain region and between the first gate structure and the second gate structure;
recessing the first and second gate electrode layers, and recessing the first and second sidewall spacers, thereby forming a first space over the recessed first gate electrode layer and the recessed first sidewall spacers and a second space over the recessed gate electrode layer and the recessed second sidewall spacers;
conformally forming a first protective layer in the first space and a second protective layer in the second space;
forming a first etch-stop layer on the first protective layer and a second etch-stop layer on the second protective layer;
removing the first insulating layer disposed over the first source/drain region, thereby forming a source/drain space;
filling the source/drain space with a conductive material;
recessing the filled conductive material by partially etching the filled conductive material below an upper surface of the second etch-stop layer, thereby forming a source/drain contact layer made of the conductive material; and
forming a third etch-stop layer over the source/drain contact layer.

8. The method of claim 7 , wherein a first depth of the first space above the first sidewall spacers is smaller than a second depth of the first space above the first gate electrode layer.

9. The method of claim 7 , wherein:
the first and second protective layers are made of a first insulating material,
the first and second etch-stop layers are made of a second insulating material different from the first insulating material, and
the third etch-stop layer is made of a third insulating material different from the first and second insulating materials.

10. The method of claim 9 , wherein, in the forming the first and second protective layers and the forming the first and second etch-stop layers:
a blanket layer of the first insulating material is conformally formed to partially fill the first and second spaces and to be in direct contact with the recessed first gate electrode layer, the recessed first sidewall spacers, the recessed gate electrode layer and the recessed second sidewall spacers;
a blanket layer of the second insulating material is formed on the blanket layer of the first insulating material to fully fill the first and second spaces; and
a planarization operation is performed to remove upper portions of the blanket layer of the first insulating material and the blanket layer of the second insulating material, thereby exposing part of the first insulating material.

11. The method of claim 7 , wherein:
the first and second protective layers are in direct contact with the recessed first gate electrode and the recessed second gate electrode, and made of at least one selected the group consisting of AlO, AlON and AlN,
the first and second etch-stop layers are made of at least one selected the group consisting of SiN and SiON, and
the third etch-stop layer is made of at least one selected the group consisting of SiC and SiOC.

12. The method of claim 7 , wherein the first and second gate electrode layers are first recessed, and then the first and second sidewall spacers are recessed.

13. The method of claim 7 , further comprising forming a second insulating layer after the third etch-stop layer is formed.

14. The method of claim 13 , further comprising:
patterning the second insulating layer and the first etch-stop layer by using a first etching process; and
patterning the first protective layer by using a second etching process, thereby forming a contact hole over the first gate electrode layer,
wherein the first protective layer functions as an etch-stop layer for the first etching process.

15. The method of claim 14 , wherein the second etching process includes a wet etching process.

16. The method of claim 13 , further comprising patterning the second insulating layer and the third etch-stop layer, thereby forming a contact hole over the source/drain contact layer.

17. A method of manufacturing a semiconductor device, the method comprising:
forming a gate structure over a substrate, the gate structu

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Shen Hsiang Ku
• Lu Chih Wei
• Chen Janet
• Yeh Jeng Ya David

Classifications

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H01L21/31111

  Electricity · mapped topic