Semiconductor device

Patent metadata

Field	Value
Publication number	US-10763335-B2
Application number	US-201816203197-A
Country	US
Kind code	B2
Filing date	Nov 28, 2018
Priority date	Jun 25, 2018
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

A semiconductor device includes a substrate having an active pattern therein, a gate electrode extending across the active pattern and a source/drain region on the active pattern laterally adjacent the gate electrode. The device further includes a contact structure including a first contact on the source/drain region, a second contact on the first contact and a spacer on sidewalls of the first and second contacts.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate having an active pattern therein;
a gate electrode extending across the active pattern;
a source/drain region on the active pattern laterally adjacent the gate electrode;
a contact structure comprising:
a first contact on the source/drain region;
a second contact on the first contact;
a spacer on sidewalls of the first and second contacts and having an upper surface coplanar with an upper surface of the second contact;

a wiring line electrically connected to the contact structure; and
a via disposed between the contact structure and the wiring line and connecting the wiring line and the contact structure,
wherein the first and second contacts are conductors.

2. The semiconductor device according to claim 1 , wherein the contact structure further comprises an insulation layer between the second contact and the spacer.

3. The semiconductor device according to claim 1 , wherein the gate electrode longitudinally extends along a first direction and wherein a maximum width of the first contact along the first direction is greater than a maximum width of the second contact along the first direction.

4. The semiconductor device according to claim 1 , wherein the first contact comprises a conductive pattern and a barrier pattern interposed between the conductive pattern and the spacer and between the conductive pattern and the source/drain region.

5. The semiconductor device according to claim 4 , wherein an upper surface of the barrier pattern is at a different level than an upper surface of the conductive pattern.

6. The semiconductor device according to claim 4 , wherein an upper portion of the conductive pattern covers an upper surface of the barrier pattern.

7. The semiconductor device according to claim 4 , wherein the barrier pattern has a first upper surface and a second upper surface, wherein the second contact contacts the second upper surface, and wherein the second upper surface of the barrier pattern is lower than the first upper surface of the barrier pattern.

8. The semiconductor device according to claim 1 , further comprising a gate contact electrically connected to the gate electrode, wherein the gate electrode longitudinally extends along a first direction, wherein the first contact comprises a first portion and a second portion adjacent to each other along the first direction, wherein the first portion of the first contact is adjacent to the gate contact in a second direction transverse to the first direction and wherein the second contact is disposed on the second portion of the first contact.

9. The semiconductor device according to claim 8 , wherein an upper surface of the second contact is coplanar with an upper surface of the gate contact, and wherein an upper surface of the first contact is lower than a lower surface of the gate contact.

10. A semiconductor device comprising:
a substrate having an active pattern therein;
a gate electrode extending across the active pattern;
a source/drain region on the active pattern laterally adjacent the gate electrode;
a gate contact electrically connected to the gate electrode; and
a contact structure electrically connected to the source/drain region and comprising:
a first contact on the source/drain regions;
a second contact on the first contact; and
a spacer on sidewalls of the first and second contacts,

wherein an upper surface of the second contact is coplanar with an upper surface of the gate contact and wherein an upper surface of the first contact is lower than a lower surface of the gate contact,
wherein the first contact comprises a conductive pattern and a barrier pattern interposed between the conductive pattern and the spacer and between the conductive pattern and the source/drain region, and
wherein the gate contact, the first contact and the second contact are conductors.

11. The semiconductor device according to claim 10 , wherein the contact structure further comprises an insulation layer between the second contact and the spacer.

12. The semiconductor device according to claim 10 , wherein the gate electrode longitudinally extends along a first direction, wherein the first contact includes a first portion and a second portion adjacent to each other in the first direction, wherein the first portion of the first contact is adjacent to the gate contact in a second direction transverse to the first direction and wherein the second contact is disposed on the second portion of the first contact.

13. The semiconductor device according to claim 10 , wherein the gate electrode longitudinally extends along a first direction and wherein a maximum width of the first contact along the first direction is greater than a maximum width of the second contact along the first direction.

14. A semiconductor device comprising:
a substrate having an active pattern therein;
a gate electrode longitudinally extending across the active pattern along a first direction;
a source/drain region on the active pattern laterally adjacent the gate electrode; and
a contact structure comprising:
a first contact on the source/drain region;

a second contact on the first contact and having a maximum width less than a maximum width of the first contact along the first direction; and
an insulation layer on a sidewall of the first contact,
wherein the first and second contacts are conductors, and
wherein the contact structure further comprises a spacer on sidewalls of the first and second contacts and wherein the insulation layer is interposed between the second contact and the spacer.

15. The semiconductor device according to claim 14 , wherein the insulation layer covers a portion of an upper surface of the first contact and a sidewall of the second contact.

16. The semiconductor device according to claim 14 , further comprising a gate contact electrically connected to the gate electrode, wherein the first contact comprises a first portion and a second portion adjacent to each other in the first direction, wherein the first portion of the first contact is adjacent to the gate contact in a second direction transverse to the first direction and wherein the second contact is disposed on the second portion of the first contact.

17. The semiconductor device according to claim 16 , wherein an upper surface of the second contact is coplanar with an upper surface of the gate contact and wherein an upper surface of the first contact is lower than a lower surface of the gate contact.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chung Wonkeun
• Lee Heonbok
• Shin Chunghwan
• Chai Youngsuk
• Hyun Sangjin

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title