Fan out system in package and method for forming the same

Patent metadata

Field	Value
Publication number	US-9583472-B2
Application number	US-201514637109-A
Country	US
Kind code	B2
Filing date	Mar 3, 2015
Priority date	Mar 3, 2015
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), stacked die between the first and second RDLs, and conductive pillars extending between the RDLs. A molding compound may encapsulate the stacked die and conductive pillars between the first and second RDLs.

First claim

What is claimed is:

1. A package comprising:
a first redistribution layer (RDL) including a first interior side and first exterior side;
a first top die bonded to the first interior side of the first RDL;
a second RDL under the first RDL, the second RDL including a second interior side and second exterior side;
a bottom die bonded to the second interior side of the second RDL, wherein the first top die is stacked on the bottom die and the first top die is not directly electrically coupled with the bottom die;
a second top die bonded to the first interior side of the first RDL, wherein the first and second top die are attached to the bottom die, and the first and second top die together occupy a larger area than the bottom die;
a plurality of conductive pillars extending from the first interior side of the first RDL to the second interior side of the second RDL; and
a molding compound located between the first interior side of the first RDL and the second interior side of the second RDL, wherein the molding compound encapsulates the plurality of conductive pillars, the first top die, the second top die, and the bottom die between the first interior side and the second interior side.

2. The package of claim 1 , further comprising a plurality of conductive bumps on the second exterior side of the second RDL.

3. The package of claim 1 , further comprising a device bonded to the first exterior side of the first RDL.

4. The package of claim 3 , wherein the device is selected from the group consisting of a lid, a heat spreader, a passive component, an integrated circuit die, and an other package.

5. The package of claim 1 , wherein the molding compound is a continuous layer of uniform composition between the first interior side of the first RDL and the second interior side of the second RDL and encapsulating the plurality of the conductive pillars the first top die, the second top die, and the bottom die.

6. The package of claim 1 , wherein the bottom die is attached to the first and second top die with a die attach film or thermal enhanced tape.

7. The package of claim 1 , wherein:
the first top die includes a front side with contact pads and a back side that does not include contact pads;
the bottom die includes a front side with contact pads and a back side that does not include contact pads; and
the front side of the first top die is bonded to the first RDL, and the front side of the bottom die is bonded to the second RDL.

8. The package of claim 7 , wherein the back side of the first top die faces the back side of the bottom die.

9. The package of claim 8 , wherein the back side of the bottom die is attached to the back sides of the first and second top die with a die attach film.

10. The package of claim 1 , further comprising a second bottom die bonded to the second interior side of the second RDL, wherein the first top die is stacked on the bottom die and the second bottom die.

11. The package of claim 1 , wherein the first top die comprises a memory device, and the bottom die comprises a logic device.

12. The package of claim 1 , wherein the second RDL includes a redistribution line directly on a contact pad of the bottom die.

13. The package of claim 1 , wherein a conductive bump on the first top die is bonded to a contact pad of the first RDL.

14. The package of claim 13 , wherein a layer selected from the group consisting of a non-conductive paste (NCP) and non-conductive film (NCF) laterally surrounds the conductive bump.

15. The package of claim 13 , wherein an anisotropic conductive film is directly between the conductive bump on the first top die and the contact pad of the first RDL.

16. The package of claim 1 , further comprising a passive component bonded to the first interior side of the first RDL.

17. The package of claim 16 , wherein the passive component is bonded to the second interior side of the second RDL.

18. The package of claim 17 , wherein the passive component is integrated as a part of a pattern of the plurality of conductive pillars.

Assignees

• Apple Inc

Inventors

• Chung Chih-Ming
• Zhai Jun
• Yang Yizhang

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/0198

  batch processes · CPC title