Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof

Patent metadata

Field	Value
Publication number	US-9396300-B2
Application number	US-201414157364-A
Country	US
Kind code	B2
Filing date	Jan 16, 2014
Priority date	Jan 16, 2014
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof are disclosed. In some embodiments, a method of packaging a plurality of semiconductor devices includes providing a first die, and coupling second dies to the first die. An electrical connection is formed between the first die and each of the second dies. A portion of each of the electrical connections is disposed between the second dies.

First claim

What is claimed is:

1. A method of packaging a plurality of semiconductor devices, the method comprising:
providing a first die, the first die including a first major surface;
mounting a plurality of second dies directly to the first major surface of the first die; and
forming an electrical connection between the first die and each of the plurality of second dies, wherein a portion of each of the electrical connections is above the first die and extends in a direction orthogonal to the first major surface and is disposed between the plurality of second dies.

2. The method according to claim 1 , wherein forming the portion of each of the electrical connections comprises forming through-vias.

3. The method according to claim 2 , wherein forming the through-vias comprises forming the through-vias in a third die or an interposer, and wherein forming the portions of each of the electrical connections comprises coupling the third die or the interposer between two of the plurality of second dies.

4. The method according to claim 3 , wherein forming the through-vias comprises forming vertical electrical connections, and wherein the method further comprises:
coupling the first die to a carrier;
forming a first molding compound around the first die;
coupling the plurality of second dies and the third die or the interposer to the first die, wherein portions of the first die are electrically coupled to the through-vias in the third die or the interposer;
forming a second molding compound around the plurality of second dies and the third die or the interposer;
forming horizontal electrical connections over the second molding compound, the plurality of second dies, and the third die or the interposer, wherein portions of the horizontal electrical connections are electrically coupled to the through-vias in the third die or the interposer;
removing the carrier; and
coupling a plurality of conductors to the horizontal electrical connections.

5. The method according to claim 2 , wherein forming the through-vias comprises disposing the through-vias in a molding compound disposed between the plurality of second dies.

6. The method according to claim 5 , wherein forming the through-vias comprises plating the through-vias over a first carrier, wherein forming the through-vias comprises forming vertical electrical connections, and wherein the method further comprises:
coupling the plurality of second dies over the first carrier;
forming the molding compound between the plurality of second dies and the through-vias;
forming horizontal electrical connections over the molding compound, the plurality of second dies, and the through-vias, wherein portions of the horizontal electrical connections are electrically coupled to the through-vias;
removing the first carrier;
coupling a second carrier to the horizontal electrical connections; and
coupling the first die to the plurality of second dies and the through-vias, wherein portions of the first die are electrically coupled to the through-vias.

7. The method according to claim 6 , wherein forming the molding compound comprises forming a first molding compound, and wherein the method further comprises:
forming a second molding compound around the first die;
removing the second carrier; and
coupling a plurality of conductors to the horizontal electrical connections.

8. A packaged semiconductor device, comprising:
a first die having a major surface;
a plurality of second dies mounted directly on the major surface of the first die; and
a plurality of electrical connections disposed between the first die and each of the plurality of second dies, wherein a portion of each of the plurality of electrical connections is directly over the first die and extends in a direction orthogonal to the major surface of the first die and is disposed between the plurality of second dies.

9. The packaged semiconductor device according to claim 8 , wherein the portions of the plurality of electrical connections comprise vertical electrical connections of the packaged semiconductor device.

10. The packaged semiconductor device according to claim 9 , wherein the first die comprises an input/output interface, and wherein the vertical electrical connections are electrically coupled to the input/output interface of the first die.

11. The packaged semiconductor device according to claim 9 , wherein the vertical electrical connections comprise through-vias disposed in a molding compound.

12. The packaged semiconductor device according to claim 9 , further comprising a third die or an interposer disposed between two of the plurality of second dies, wherein the vertical electrical connections comprise through-vias disposed in the third die or the interposer.

13. The packaged semiconductor device according to claim 9 , wherein the plurality of electrical connections further comprise horizontal electrical connections, and wherein portions of the horizontal electrical connections are electrically coupled to the vertical electrical connections.

14. The packaged semiconductor device according to claim 13 , wherein the horizontal electrical connections are disposed on a side of the packaged semiconductor device proximate the plurality of second dies.

15. The packaged semiconductor device according to claim 13 , wherein the horizontal electrical connections comprise a redistribution layer (RDL) or a post passivation interconnect (PPI) structure.

16. The packaged semiconductor device according to claim 13 , further comprising a plurality of conductors coupled to the horizontal electrical connections.

17. The packaged semiconductor device according to claim 8 , further comprising a first molding compound disposed around the first die, and a second molding compound disposed around the plurality of second dies and the portion of the plurality of electrical connections disposed between the plurality of second dies.

18. The packaged semiconductor device according to claim 8 , wherein the first die is adapted to perform a first function, wherein the plurality of second dies are adapted to perform a second function, the second function being different than the first function, and wherein the packaged semiconductor device comprises a system on a chip (SOC).

19. A device comprising:
a first die, the first die having a first major surface including contact pads disposed thereon;
a plurality of through via structures over and vertically aligned with the first major surface and electrically coupled to respective contact pads;
a second die having a topmost surface positioned on a first plane, the first plane being over and parallel to the first major surface, the second die having a bottommost surface positioned on a second plane parallel to the first plane, the second die being electrically coupled to a first subset of the plurality of through via structures;
a third die having a topmost surface positioned on the first plane the third die being electrically coupled to a second subset of the plurality of through via structures, wherein the plurality of through via structures extend from the first plane to the second plane.

20. The device of claim 19 , wherein the through via structures extend through an element selected from the group consisting of a die substrate, an interposer, and a molding compound.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Wang Chuei-Tang
• Liu Monsen
• Yu Chen-Hua

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title