Redundant array of independent NAND for a three-dimensional memory array

Patent metadata

Field	Value
Publication number	US-10318378-B2
Application number	US-201615053719-A
Country	US
Kind code	B2
Filing date	Feb 25, 2016
Priority date	Feb 25, 2016
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

The present disclosure includes a redundant array of independent NAND for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, and the parity portion of the RAIN stripe in each respective page comprises only a portion of that respective page.

First claim

What is claimed is:

1. An apparatus, comprising:
a three-dimensional array of memory cells, wherein:
the array includes a plurality of physical pages of memory cells and a plurality of groups of memory cells, wherein each respective group includes a different portion of each respective physical page and each respective group has a three-dimensional stair step structure;
a number of the plurality of physical pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, wherein each respective one of the number of physical pages includes a parity portion of a different RAIN stripe such that the parity portion of each different RAIN stripe is included in a single physical page; and
the parity portion of the RAIN stripe in each respective physical page comprises only a portion of that respective physical page; and

a plurality of string drivers, wherein each respective string driver is associated with a different one of the groups of memory cells having the three-dimensional stair step structure.

2. The apparatus of claim 1 , wherein the parity portion of the RAIN stripe in each respective physical page of memory cells comprises one-fourth of that respective physical page.

3. The apparatus of claim 1 , wherein the plurality of groups of memory cells are tile groups.

4. The apparatus of claim 1 , wherein a remaining portion of each respective physical page of memory cells that includes a parity portion of the RAIN stripe includes user data.

5. The apparatus of claim 1 , wherein the parity portion of the RAIN stripe in each respective physical page of memory cells comprises more than one-fourth of that respective physical page.

6. The apparatus of claim 1 , wherein the parity portion of the RAIN stripe in each respective physical page of memory cells comprises less than one-fourth of that respective physical page.

7. An apparatus, comprising:
a three-dimensional array of memory cells, wherein:
the array includes a plurality of groups of memory cells and a plurality of physical pages of memory cells, wherein each respective group includes a different portion of each respective physical page and each respective group has a three-dimensional stair step structure;
a number of the plurality of physical pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, wherein each respective one of the number of physical pages includes a parity portion of a different RAIN stripe such that the parity portion of each different RAIN stripe is included in a single physical page; and
a size of the parity portion of each different RAIN stripe is less than a size of the physical page that includes that parity portion; and

a plurality of string drivers, wherein each respective string driver is associated with a different one of the groups of memory cells having the three-dimensional stair step structure.

8. The apparatus of claim 7 , wherein the size of the parity portion of each different RAIN stripe corresponds to a size of each different portion of each respective physical page of memory cells included in each respective group of memory cells.

9. The apparatus of claim 7 , wherein each RAIN stripe is configured to provide protection for each of the plurality of groups of memory cells.

10. The apparatus of claim 7 , wherein the parity portion of each different RAIN stripe is included in a same one of the plurality of groups of memory cells.

11. The apparatus of claim 7 , wherein the parity portion of each different RAIN stripe are included in different ones of the plurality of groups of memory cells.

12. The apparatus of claim 7 , wherein the apparatus includes a controller coupled to the three-dimensional array, wherein the controller includes a RAIN component configured to:
program data to each RAIN stripe; and
sense data stored in each RAIN stripe.

13. A method of operating memory, comprising:
storing a parity portion of a redundant array of independent NAND (RAIN) stripe in a first portion of a number of physical pages of memory cells in a plurality of groups of memory cells in a three-dimensional array of memory cells, wherein:
each respective group includes a different portion of each respective physical page and each respective group has a three-dimensional stair step structure; and
each respective one of the number of physical pages includes a parity portion of a different RAIN stripe such that the parity portion of each different RAIN stripe is included in a single physical page;

storing user data in a second portion of the number of physical pages; and
controlling selection of the memory cells using a plurality of string drivers, wherein each respective string driver is associated with a different one of the groups of memory cells having the three-dimensional stair step structure.

14. The method of claim 13 , wherein:
the parity portion of the RAIN stripe is stored in one-fourth of each respective physical page of memory cells; and
the user data is stored in three-fourths of each respective physical page.

15. The method of claim 13 , wherein:
the first portion of each respective physical page of memory cells is a portion of a first one of the groups of memory cells; and
the second portion of each respective physical page of memory cells is a portion of a second one of the groups of memory cells.

16. The method of claim 13 , wherein the method includes, upon a failure occurring in the three-dimensional array:
sensing data stored in the parity portion of the RAIN stripe in each respective physical page; and
recovering user data stored in the array using the sensed data.

17. A method of operating memory, comprising:
storing a plurality of redundant array of independent NAND (RAIN) stripes in a plurality of physical pages of memory cells in a plurality of groups of memory cells in a three-dimensional memory array, wherein:
each respective group includes a different portion of each respective physical page and each respective group has a three-dimensional stair step structure;
each respective physical page stores a parity portion of a different RAIN stripe such that the parity portion of each different RAIN stripe is included in a single physical page; and
the parity portion of the RAIN stripe stored in each respective physical page is stored in less than all of the physical page; and

controlling selection of the memory cells using a plurality of string drivers, wherein each respective string driver is associated with a different one of the groups of memory cells having the three-dimensional stair step structure.

18. The method of claim 17 , wherein the method includes providing protection for each of the plurality of groups of memory cells by storing the RAIN stripes in the plurality of physical pages of memory cells.

19. The method of claim 18 , wherein providing protection for each of the plurality of groups of memory cells includes providing protection for all user data stored in each of the plurality of groups.

20. The method of claim 18 , wherein providing protection for each of the plurality of groups of memory cells includes providing protection for each of the plurality of groups of memory cells against a failure that may occur in one of the groups.

21. The method of claim 17 , wherein the method includes providing protection against an access line to access line short that may occur in one of the groups of memory cells by storing the RAIN stripes in the plurality of physical pages of memory cells.

Assignees

• Micron Technology Inc

Inventors

• Hoei Jung Sheng
• Ratnam Sampath K
• Padilla Renato C
• Muchherla Kishore K
• Parthasarathy Sivagnanam
• Feeley Peter

Classifications

• G06F3/064

  Management of blocks · CPC title

• G06F3/0608

  Saving storage space on storage systems · CPC title

• G06F11/10

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F11/1072 Primary

  in multilevel memories · CPC title