Acceleration of data queries in memory

Patent metadata

Field	Value
Publication number	US-11289166-B2
Application number	US-202016984452-A
Country	US
Kind code	B2
Filing date	Aug 4, 2020
Priority date	Aug 4, 2020
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.

First claim

What is claimed is:

1. An apparatus, comprising:
an array of memory cells; and
processing circuitry configured to:
receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host;
search portions of the array of memory cells for the particular data corresponding to the search key;
determine data stored in the portions of the array of memory cells that corresponds more closely to the search key than other data stored in the portions of the array of memory cells;
perform an error correction operation on the data determined to correspond more closely to the search key;
determine data stored in the portions of the array of memory cells that matches the search key after performing the error correction operation on the data determined to correspond more closely to the search key; and
transfer the data that matches the search key to the host.

2. The apparatus of claim 1 , wherein the processing circuitry is configured to determine the data that matches the search key based on an amount of current conducted by the portions of the array of memory cells.

3. The apparatus of claim 2 , wherein the amount of current conducted by a portion of the array of memory cells is greater when the memory cells in that portion of the array store data corresponding to bits in the search key than when the memory cells in that portion of the array store data that does not correspond to the bits in the search key.

4. The apparatus of claim 2 , wherein the data stored in a portion of the array of memory cells that conducts a greater amount of current than other portions of the array is determined to be the data that matches the search key.

5. The apparatus of claim 1 , wherein the array and the processing circuitry are formed on a same chip of the apparatus.

6. The apparatus of claim 1 , wherein the circuitry comprises a page buffer.

7. The apparatus of claim 1 , wherein no data stored in the portions of the array of memory cells that does not match the search key is transferred to the host.

8. An apparatus, comprising:
an array of memory cells; and
processing circuitry configured to:
receive, from a host, a query for data stored in the array of memory cells, wherein the data corresponds to a search key generated by the host;
search portions of the array of memory cells for the data;
determine data stored in the portions of the array of memory cells that corresponds more closely to the search key than other data stored in the portions of the array of memory cells;
perform an error correction operation on the data determined to correspond more closely to the search key;
determine data stored in the portions of the array of memory cells that matches the query after performing the error correction operation on the data determined to correspond more closely to the search key; and
transfer, to the host, only the data that matches the query.

9. The apparatus of claim 8 , wherein the array of memory cells comprises a database.

10. The apparatus of claim 8 , wherein the array of memory cells is a three-dimensional NAND array of memory cells.

11. The apparatus of claim 8 , wherein the portions of the array of memory cells comprise strings of memory cells.

12. The apparatus of claim 8 , wherein the processing circuitry comprises CMOS under array circuitry.

13. The apparatus of claim 8 , wherein the processing circuitry is configured to determine the data stored in the portions of the array of memory cells that matches the query by:
applying a voltage to each of the portions of the array of memory cells; and
determining the data that matches the query based on an amount of current conducted by each respective portion of the array of memory cells upon the voltage being applied thereto.

14. The apparatus of claim 8 , wherein:
the array of memory cells comprises a plurality of planes of memory cells; and
the processing circuitry comprises a plurality of page buffers;
wherein each respective one of the page buffers corresponds to a different one of the planes of memory cells.

15. A method, comprising:
receiving, by a memory device from a host, a query for particular data, wherein the particular data corresponds to a search key generated by the host;
searching, by the memory device, portions of the memory device for the particular data;
counting, by the memory device, a quantity of bits in each of the portions of the memory device that match a corresponding bit in the search key, and correcting, by the memory device, errors in the bits in the portions of the memory device, to determine data stored in the portions of the memory device that matches the query; and
transferring the data that matches the query to the host and refraining from transferring nonmatching data to the host.

16. The method of claim 15 , wherein searching the portions of the memory device for the particular data includes:
sensing, by the memory device, data stored in the portions of the memory device;
performing, by the memory device, an error correction operation on the sensed data; and
decrypting, by the memory device, the sensed data after performing the error correction operation on the sensed data.

17. The method of claim 15 , wherein the method includes encrypting, by the memory device, data stored in the portions of the memory device.

18. The method of claim 15 , wherein the method includes searching each of the portions of the memory device for the particular data in parallel.

19. A method, comprising:
generating, by a host, a search key denoting particular data;
setting, by the host, a mismatch bit count for a query for the particular data;
sending, to a memory device by the host, the query for the particular data; and
receiving data that matches the query at the host from the memory device or from a buffer coupled to the host, wherein the data that matches the query is based at least in part on results of a search at the memory device that includes a comparison of the search key and determination of matching data, relative to the search key, stored within the memory device.

20. The method of claim 19 , wherein the data that matches the query comprises data whose quantity of bits that match a corresponding bit in the search key is greater than the mismatch bit count.

21. The method of claim 19 , wherein the query sent by the host is unencrypted.

22. The method of claim 19 , wherein the data that matches the query received at the host is encrypted.

23. The method of claim 22 , wherein the method includes decrypting, by the host, the encrypted data that matches the query.

24. A system, comprising:
a host; and
a memory device coupled to the host;
wherein the host is configured to:
generate a search key to denote particular data; and
send a query for the particular data to the memory device; and

wherein the memory device is configured to, in response to receiving the query:
search portions of the memory device for the particular data;
count a number of bits in each portion of the memory device that match the particular data denoted in the search key, and correct errors in the bits in the portions of the memory device, to determine data stored in the portions of the memory device that matches the query; and
transfer the data that matches the query to the host and refrain from transferring nonmatching data to the host.

25. The

Assignees

• Micron Technology Inc

Inventors

• Helm Mark A
• Pawlowski Joseph T

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C15/046

  using non-volatile storage elements · CPC title

• G11C16/12 Primary

  Programming voltage switching circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title