Approach to child block pinning

Patent metadata

Field	Value
Publication number	US-12367331-B2
Application number	US-202217671696-A
Country	US
Kind code	B2
Filing date	Feb 15, 2022
Priority date	Feb 15, 2022
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

A hybrid block pinning optimization system includes a small-block processing module that processes a parent-level hierarchy including a plurality of child-level blocks and places a plurality of initial child-block pins corresponding to the child-level blocks. A child processing module places a logic element at a location within a given child block based on the placement of the initial child pins, discards the plurality of initial child pins while maintaining the location of the logic element, places at least one optimized child pin based at least in part on the location of the at least one logic element, and performs an abstraction operation on the logic element while maintaining the at least one child pin within the child blocks. A hierarchical large block synthesis (hLBS) processing module performs an hLBS operation to dissolve the plurality of child blocks, while maintaining the at least one optimized child pin.

First claim

What is claimed is:

1. A hybrid block pinning optimization system comprising:
small-block processing module configured to process a parent-level hierarchy including a plurality of child-level blocks and to place a plurality of initial child-block pins corresponding to the child-level blocks;
a child processing module configured to place at least one logic element at a location within a given child block among the plurality of child blocks based on the placement of the initial child pins, discard the plurality of initial child pins while maintaining the location of the at least one logic element, place at least one optimized child pin based at least in part on the location of the at least one logic element, and perform an abstraction operation on the at least one logic element while maintaining the at least one child pin within the child blocks; and
a hierarchical large block synthesis (hLBS) module configured to perform an hLBS operation to dissolve the plurality of child blocks, while maintaining the at least one optimized child pin.

2. The block pinning optimization system according to claim 1 , wherein the small-block processing module determines the placement of the initial child pins is based at least in part on timing requirements of the parent-level hierarchy.

3. The block pinning optimization system according to claim 2 , wherein the placement of the at least one logic element within a given child block is based on a route timing requirement between the at least one logic element located in the given child block and the initial child block pin of the given child block.

4. The block pinning optimization system according to claim 3 , wherein a route segment between the at least one logic element and the initial child pin defines a scenic routing path segment.

5. The block pinning optimization system according to claim 4 , wherein the child processing module is further configured to discard the initial child pins and the scenic routing path segment, while maintaining the at least one logic element.

6. The block pinning optimization system according to claim 5 , wherein the child processing module places an optimized child pin on the logic gates placed within the child blocks.

7. The block pinning optimization system according to claim 6 , wherein the child processing module performs a child block abstraction operation to dissolve the at least one logic element in the child blocks while maintain the placement of the optimized child pins.

8. The block pinning optimization system according to claim 7 , wherein the child processing module creates a direct signal routing path between a first optimized child pin placed in a first child block among the plurality of child blocks and a second optimized child pin located in a second child block among the plurality of child blocks.

9. A computer-implemented method of optimizing placement of child-block pins in a parent-level hierarchy, the method comprising:
placing, by a small-block processing module, a plurality of initial child-block pins corresponding to child-level blocks included in the parent-level hierarchy;
placing, by a child processing module, at least one logic element at a location within a given child block among the plurality of child blocks based on the placement of the initial child pins;
discarding, by the child processing module, the plurality of initial child pins while maintaining the location of the at least one logic element;
placing, by the child processing module, at least one optimized child pin based at least in part on the location of the at least one logic element;
performing, by the child processing module, an abstraction operation on the at least one logic element while maintaining the at least one child pin within the child blocks; and
performing, by a hierarchical large block synthesis (hLBS) module, an hLBS operation to dissolve the plurality of child blocks, while maintaining the at least one optimized child pin.

10. The computer-implemented method according to claim 9 , further comprising determining, by the small-block processing module, the placement of the initial child pins based at least in part on timing requirements of the parent-level hierarchy.

11. The computer-implemented method according to claim 10 , further comprising determining the placement of the at least one logic element within a given child block based on a route timing requirement between the at least one logic element located in the given child block and the initial child block pin of the given child block.

12. The computer-implemented method according to claim 11 , wherein a route segment between the at least one logic element and the initial child pin defines a scenic routing path segment.

13. The computer-implemented method according to claim 12 , further comprising discarding, by the child processing module, the initial child pins and the scenic routing path segment, while maintaining the at least one logic element.

14. The computer-implemented method according to claim 13 , further comprising placing, by the child processing module, an optimized child pin on the logic gates placed within the child blocks.

15. The computer-implemented method according to claim 14 , further comprising performing, by the child processing module, a child block abstraction operation to dissolve the at least one logic element in the child blocks while maintain the placement of the optimized child pins.

16. The computer-implemented method according to claim 15 , further comprising creating, by the child processing module, a direct signal routing path between a first optimized child pin placed in a first child block among the plurality of child blocks and a second optimized child pin located in a second child block among the plurality of child blocks.

17. A computer program product to control a controller to optimize placement of child-block pins in a parent-level hierarchy, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by the controller to perform operations comprising:
placing, by a small-block processing module, a plurality of initial child-block pins corresponding to child-level blocks included in the parent-level hierarchy;
placing, by a child processing module, at least one logic element at a location within a given child block among the plurality of child blocks based on the placement of the initial child pins;
discarding, by the child processing module, the plurality of initial child pins while maintaining the location of the at least one logic element;
placing, by the child processing module, at least one optimized child pin based at least in part on the location of the at least one logic element; and
performing, by the child processing module, an abstraction operation on the at least one logic element while maintaining the at least one child pin within the child blocks; and
performing, by a hierarchical large block synthesis (hLBS) module, an hLBS operation to dissolve the plurality of child blocks, while maintaining the at least one optimized child pin.

18. The computer program product according to claim 17 , wherein the operations further comprise:
determining, by the small-block processing module, the placement of the initial child pins based at least in part on timing requirements of the parent-level hierarchy; and
determining the placement of the at least one logic element within a given child block based on a route timing requirement between the at least one logic element located in the given

Assignees

• IBM

Inventors

• Surprise Jesse Peter
• Herkel Eduard
• Geva Ofer
• Hasan Faisal

Classifications

• G06F30/3947

  global · CPC title

• G06F30/3953

  detailed · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title