Cross-hierarchical block pin placement

Patent metadata

Field	Value
Publication number	US-10902175-B1
Application number	US-201916567118-A
Country	US
Kind code	B1
Filing date	Sep 11, 2019
Priority date	Sep 11, 2019
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

Methods, systems and computer program products for providing cross-hierarchical block pin placement are provided. Aspects include designating potential pin placements by aligning output pins of each of a first set of bottom-level hierarchical blocks positioned within one or more middle-level hierarchical blocks to an edge of a respective middle-level hierarchical block. Responsive to determining that each of a first subset of a second set of bottom-level hierarchical blocks having input pins that correspond to the output pins of the first set of bottom-level hierarchical blocks are positioned within a respective middle-level hierarchical block that has a cross hierarchical alignment, aspects include placing pins at one or more of the potential pin placements. Aspects also include placing a set of pins based on aligning input pins of a second subset of the second set of bottom-level hierarchical blocks to an edge of a respective middle-level hierarchical block.

First claim

What is claimed is:

1. A computer-implemented method comprising:
designating a first set of potential pin placements by aligning output pins of each of a first set of bottom-level hierarchical blocks positioned within one or more middle-level hierarchical blocks to an edge of a respective middle-level hierarchical block, wherein the one or more middle-level hierarchical blocks are positioned within a top-level hierarchical block of a circuit design;
responsive to determining that each of a first subset of a second set of bottom-level hierarchical blocks having input pins that correspond to the output pins of the first set of bottom-level hierarchical blocks are positioned within a respective middle-level hierarchical block that has a cross hierarchical alignment, placing a corresponding one or more middle-level hierarchical pins at one or more of the first set of potential pin placements; and
placing a set of middle-level hierarchical pins at a second set of potential pin placements designated by aligning input pins of a second subset of the second set of bottom-level hierarchical blocks to an edge of a respective middle-level hierarchical block.

2. The computer-implemented method of claim 1 further comprising:
flattening through one or more latches and buffers within the circuit design to remove hierarchical boundaries along one or more routes associated with the one or more latches and buffers.

3. The computer-implemented method of claim 2 further comprising:
for each net between an output pin of a bottom-level hierarchical block and an input pin of a corresponding bottom-level hierarchical block, tagging the net with a use layer; and
wherein each middle-level hierarchical pin is placed on a respective use layer corresponding to a respective associated net.

4. The computer-implemented method of claim 1 , wherein designating the first set of potential pin placements by aligning output pins of each of a first set of bottom-level hierarchical blocks positioned within one or more middle-level hierarchical blocks to an edge of a respective middle-level hierarchical block comprises, for each of the first set of bottom-level hierarchical blocks:
identifying a target direction, wherein the target direction comprises a north, south, east or west direction of an adjacent middle-level hierarchical block to the respective middle-level hierarchical block that includes a corresponding bottom-level hierarchical block having an input pin that corresponds to the output pin of the bottom-level hierarchical block of the first set of bottom-level hierarchical blocks; and
locating a point on the edge of the middle-level hierarchical block that aligns with the output pin, wherein the edge is disposed in the target direction away from the bottom-level hierarchical block of the first set of bottom-level hierarchical blocks.

5. The computer-implemented method of claim 4 , wherein locating a point on the edge of the middle-level hierarchical block that aligns with the output pin comprises locating a point on the edge of the middle-level hierarchical block that is positioned at an intersection of the edge and perpendicular line extending from the edge to the output pin.

6. The computer-implemented method of claim 1 , wherein determining that each of a first subset of a second set of bottom-level hierarchical blocks having input pins that correspond to the output pins of the first set of bottom-level hierarchical blocks are positioned within a respective middle-level hierarchical block that has a cross hierarchical alignment comprises, for each bottom-level hierarchical block of the first subset of a second set of bottom-level hierarchical blocks, determining that:
a path of a net that extends from the input pin directly to a potential pin placement of the first set of potential pin placements associated with a bottom-level hierarchical block having a corresponding output pin does not pass through a different middle-level hierarchical block.

7. The computer-implemented method of claim 6 , wherein a path of the net that extends from the input pin directly to a potential pin placement of the first set of potential pin placements comprises a path that is of a shortest possible distance between the input pin and the potential pin placement.

8. The computer-implemented method of claim 1 , wherein the first subset of the second set of bottom-level hierarchical blocks and the second subset of the second set of bottom-level hierarchical blocks are mutually exclusive.

9. The computer-implemented method of claim 1 , wherein placing each middle-level hierarchical pin of the corresponding one or more middle-level hierarchical pins and the set of middle-level hierarchical pins comprises positioning a middle-level hierarchical pin in a position disposed between an edge of two middle-level hierarchical blocks that respectively include a bottom-level hierarchical blocks having an output pin and a corresponding bottom-level hierarchical block having an input pin to connect the two middle-level hierarchical blocks.

10. The computer-implemented method of claim 1 further comprising:
for a bottom-level hierarchical block positioned externally to all middle-level hierarchical blocks that has a net that is connected to one or more latches or buffers in middle-level hierarchical blocks other than a middle-level hierarchical block that includes a bottom-level hierarchical block that is connected to an end of the net, placing a first middle-level hierarchical pin on an edge of a first middle-level hierarchical block containing a first latch or buffer of the one or more latches or buffers; and
placing one or more additional middle-level hierarchical pins between each pair of middle-level hierarchical blocks along a path of the net.

11. A system comprising:
a memory having computer readable instructions; and
one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
designating a first set of potential pin placements by aligning output pins of each of a first set of bottom-level hierarchical blocks positioned within one or more middle-level hierarchical blocks to an edge of a respective middle-level hierarchical block, wherein the one or more middle-level hierarchical blocks are positioned within a top-level hierarchical block of a circuit design;
responsive to determining that each of a first subset of a second set of bottom-level hierarchical blocks having input pins that correspond to the output pins of the first set of bottom-level hierarchical blocks are positioned within a respective middle-level hierarchical block that has a cross hierarchical alignment, placing a corresponding one or more middle-level hierarchical pins at one or more of the first set of potential pin placements; and
placing a set of middle-level hierarchical pins at a second set of potential pin placements designated by aligning input pins of a second subset of the second set of bottom-level hierarchical blocks to an edge of a respective middle-level hierarchical block.

12. The system of claim 11 further comprising:
flattening through one or more latches and buffers within the circuit design to remove hierarchical boundaries along one or more routes associated with the one or more latches and buffers.

13. The system of claim 12 further comprising:
for each net between an output pin of a bottom-level hierarchical block and an input pin of a corresponding bottom-level hierarchical block, tagging the net with a use layer; and
wherein each middle-level hierarchical pin is placed on a respective use la

Assignees

• IBM

Inventors

• Surprise Jesse
• Strevig Iii Gerald
• Kollesar Shawn

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title