Optimization of integrated circuit physical design

Patent metadata

Field	Value
Publication number	US-9536030-B2
Application number	US-201414302484-A
Country	US
Kind code	B2
Filing date	Jun 12, 2014
Priority date	Jun 12, 2014
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

According to one embodiment of the present invention, a method for optimizing an integrated circuit design is provided. The method may include identifying one or more nets crossing a boundary between a parent block, having parent logic, and a child block, having child logic. The method may include inserting interior buffers on the nets inside of the child block and exterior buffers on the nets outside of the child block and inside of the parent block, wherein the interior buffers and the exterior buffers define a buffer pair for each of the nets. The method may further include determining a first placement for the parent logic and a second placement for the child logic, such that the buffers of the buffer pair for each net are placed substantially near to one another. The method may further include determining pin locations for the child block based on the second placement.

First claim

What is claimed is:

1. A method for optimizing an integrated circuit design, the method comprising:
identifying, by one or more computer processors, one or more nets crossing a boundary between a parent block, having parent logic, and a child block, having child logic;
inserting, by the one or more computer processors, based on a flat placement, one or more interior buffers on the one or more nets inside of the child block and one or more exterior buffers on the one or more nets outside of the child block and inside of the parent block, such that each of the one or more nets includes at least one interior buffer and at least one exterior buffer, wherein the at least one interior buffer and the at least one exterior buffer define a buffer pair for each of the one or more nets;
determining, by the one or more computer processors, a first flat placement for the parent logic and a second flat placement for the child logic such that the at least one interior buffer and the at least one exterior buffer in the buffer pair for each net are placed substantially near to one another; and
determining, by the one or more computer processors, one or more pin locations for the child block based, at least in part, on the second flat placement for the child logic.

2. The method of claim 1 , further comprising:
determining, by the one or more computer processors, a third flat placement for the child logic based, at least in part, on the one or more pin locations; and
replacing, by one or more computer processors, the second flat placement with the third flat placement.

3. The method of claim 1 , further comprising:
assigning, by the one or more computer processors, an attraction value to each buffer pair of the one or more nets.

4. The method of claim 3 , wherein determining the first flat placement and the second flat placement is based, at least in part, on the attraction value assigned to each buffer pair of the one or more nets.

5. The method of claim 1 , wherein the boundary between the parent block and the child block is an exclusive movebound.

6. The method of claim 1 , wherein determining the second flat placement comprises placing the one or more interior buffers so that the one or more interior buffers are not overlapping.

7. The method of claim 1 , wherein the one or more interior buffers and the one or more exterior buffers are circuit elements that preserve clock phase signal polarity.

8. A computer program product for optimizing an integrated circuit design, the computer program product comprising:
one or more computer-readable storage media and program instructions stored on the one or more computer-readable storage media, the program instructions comprising:
program instructions to identify one or more nets crossing a boundary between a parent block, having parent logic, and a child block, having child logic;
program instructions to insert, based on a flat placement, one or more interior buffers on the one or more nets inside of the child block and one or more exterior buffers on the one or more nets outside of the child block and inside of the parent block, such that each of the one or more nets includes at least one interior buffer and at least one exterior buffer, wherein the at least one interior buffer and the at least one exterior buffer define a buffer pair for each of the one or more nets;
program instructions to determine a first flat placement for the parent logic and a second flat placement for the child logic, such that the at least one interior buffer and the at least one exterior buffer in the buffer pair for each net are placed substantially near to one another; and
program instructions to determine one or more pin locations for the child block based, at least in part, on the second flat placement for the child logic.

9. The computer program product of claim 8 , further comprising:
program instructions to determine a third flat placement for the child logic based, at least in part, on the one or more pin locations; and
program instructions to replace the second flat placement with the third flat placement.

10. The computer program product of claim 8 , further comprising:
program instructions to assign an attraction value to each buffer pair of the one or more nets.

11. The computer program product of claim 10 , wherein determining the first flat placement and the second flat placement is based, at least in part, on the attraction value assigned to each buffer pair of the one or more nets.

12. The computer program product of claim 8 , wherein the boundary between the parent block and the child block is an exclusive movebound.

13. The computer program product of claim 8 , wherein determining the second flat placement comprises placing the one or more interior buffers so that the one or more interior buffers are not overlapping.

14. The computer program product of claim 8 , wherein the one or more interior buffers and the one or more exterior buffers are circuit elements that preserve clock phase signal polarity.

15. A computer system for optimizing an integrated circuit design, the computer system comprising:
one or more computer processors;
one or more computer-readable storage media;
program instructions stored on the computer-readable storage media for execution by at least one of the one or more processors, the program instructions comprising:
program instructions to identify one or more nets crossing a boundary between a parent block, having parent logic, and a child block, having child logic;
program instructions to insert, based on a flat placement, one or more interior buffers on the one or more nets inside of the child block and one or more exterior buffers on the one or more nets outside of the child block and inside of the parent block, such that each of the one or more nets includes at least one interior buffer and at least one exterior buffer, wherein the at least one interior buffer and the at least one exterior buffer define a buffer pair for each of the one or more nets;
program instructions to determine a first flat placement for the parent logic and a second flat placement for the child logic, such that the at least one interior buffer and the at least one exterior buffer in the buffer pair for each net are placed substantially near to one another; and
program instructions to determine one or more pin locations for the child block based, at least in part, on the second flat placement for the child logic.

16. The computer system of claim 15 , further comprising:
program instructions to determine a third flat placement for the child logic based, at least in part, on the one or more pin locations; and
program instructions to replace the second flat placement with the third flat placement.

17. The computer system of claim 15 , further comprising:
program instructions to assign an attraction value to each buffer pair of the one or more nets.

18. The computer system of claim 17 , wherein determining the first flat placement and the second flat placement is based, at least in part, on the attraction value assigned to each buffer pair of the one or more nets.

19. The computer system of claim 15 , wherein the boundary between the parent block and the child block is an exclusive movebound.

20. The computer system of claim 15 , wherein determining the second flat placement comprises placing the one or more interior buffers so that the one or more interior buffers are not overlapping.

Assignees

• IBM

Inventors

• Fricke Niels
• Muuss Karsten
• Verwegen Peter
• Wandel Christoph W

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F17/5077

  Physics · mapped topic

• G06F17/5081

  Physics · mapped topic