Automated design closure with abutted hierarchy

Patent metadata

Field	Value
Publication number	US-11080456-B2
Application number	US-201916699085-A
Country	US
Kind code	B2
Filing date	Nov 28, 2019
Priority date	Nov 28, 2019
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

To increase the efficiency of electronic design automation, execute partition-aware global routing with track assignment on an electronic data structure including a small block floorplan of a putative integrated circuit design. The small block floorplan is virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks. Based on results of the executing, determine locations, on the inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in the routing, as well as required sizes of the ports. Generate a physical partitioning based on the inter-large-block boundaries; align the ports with the inter-large-block boundaries; and generate a hardware description language design structure encoding the physical partitioning.

First claim

What is claimed is:

1. A method for increasing the efficiency of electronic design automation, the method comprising:
executing partition-aware global routing with track assignment on an electronic data structure comprising a small block floorplan of a putative integrated circuit design, the small block floorplan being virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks, wherein a high cost is assigned to a route that crosses a same border twice and wherein said executing of said global routing includes applying a cost function that utilizes said assigned high cost to prevent zig-zagging of routes;
based on results of said executing, determining locations, on said inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in said routing, as well as required sizes of said ports;
generating a physical partitioning based on said inter-large-block boundaries;
aligning said ports with said inter-large-block boundaries; and
generating a hardware description language design structure encoding said physical partitioning.

2. The method of claim 1 , further comprising generating timing assertions at said port locations on said inter-large-block boundaries from top-level timing assertions.

3. The method of claim 2 , wherein said executing of said global routing includes constraining a Steiner branching point to lie within a target one of said large blocks.

4. The method of claim 3 , wherein said executing of said global routing includes, for those of said inter-large-block boundaries having multiple ones of said ports, spreading said ports to minimize routing congestion.

5. The method of claim 2 , wherein said executing of said global routing includes, for those of said inter-large-block boundaries having multiple ones of said ports, spreading said ports to minimize routing congestion.

6. The method of claim 1 , wherein said executing of said global routing includes constraining a Steiner branching point to lie within a target one of said large blocks.

7. The method of claim 6 , wherein said executing of said global routing includes, for those of said inter-large-block boundaries having multiple ones of said ports, spreading said ports to minimize routing congestion.

8. The method of claim 1 , further comprising fabricating a physical integrated circuit in accordance with said design structure.

9. A computer comprising:
a memory; and
at least one processor, coupled to said memory, and operative to increase the efficiency of electronic design automation by:
executing partition-aware global routing with track assignment on an electronic data structure comprising a small block floorplan of a putative integrated circuit design, the small block floorplan being virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks, wherein a high cost is assigned to a route that crosses a same border twice and wherein said executing of said global routing includes applying a cost function that utilizes said assigned high cost to prevent zig-zagging of routes;
based on results of said executing, determining locations, on said inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in said routing, as well as required sizes of said ports;
generating a physical partitioning based on said inter-large-block boundaries;
aligning said ports with said inter-large-block boundaries; and

generating a hardware description language design structure encoding said physical partitioning.

10. The computer of claim 9 , further comprising generating timing assertions at said port locations on said inter-large-block boundaries from top-level timing assertions.

11. The computer of claim 9 , wherein said executing of said global routing includes constraining a Steiner branching point to lie within a target one of said large blocks.

12. The computer of claim 11 , wherein said executing of said global routing includes, for those of said inter-large-block boundaries having multiple ones of said ports, spreading said ports to minimize routing congestion.

13. The computer of claim 9 , wherein said at least one processor is further operative to increase the efficiency of the electronic design automation by providing said design structure to fabrication equipment to facilitate fabrication of a physical integrated circuit in accordance with said design structure.

14. A non-transitory computer readable medium comprising computer executable instructions which when executed by a computer performing electronic design automation cause the computer to perform a method which increases the efficiency of the electronic design automation, the method comprising:
executing partition-aware global routing with track assignment on an electronic data structure comprising a small block floorplan of a putative integrated circuit design, the small block floorplan being virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks, wherein a high cost is assigned to a route that crosses a same border twice and wherein said executing of said global routing includes applying a cost function that utilizes said assigned high cost to prevent zig-zagging of routes;
based on results of said executing, determining locations, on said inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in said routing, as well as required sizes of said ports;
generating a physical partitioning based on said inter-large-block boundaries;
aligning said ports with said inter-large-block boundaries; and
generating a hardware description language design structure encoding said physical partitioning.

15. The non-transitory computer readable medium of claim 14 , wherein said method further comprises generating timing assertions at said port locations on said inter-large-block boundaries from top-level timing assertions.

16. The non-transitory computer readable medium of claim 14 , wherein said executing of said global routing includes constraining a Steiner branching point to lie within a target one of said large blocks.

17. The non-transitory computer readable medium of claim 16 , wherein said executing of said global routing includes, for those of said inter-large-block boundaries having multiple ones of said ports, spreading said ports to minimize routing congestion.

Assignees

• IBM

Inventors

• Kazda Michael
• Folberth Harald
• Villarrubia Paul G
• Held Stephan
• Saccardi Pietro

Classifications

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/30

  Circuit design · CPC title