Hierarchically aware interior pinning for large synthesis blocks

Patent metadata

Field	Value
Publication number	US-10157255-B2
Application number	US-201715823705-A
Country	US
Kind code	B2
Filing date	Nov 28, 2017
Priority date	Jun 30, 2016
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A system and a computer implemented method for interior pinning in a macro block of an integrated circuit are provided. The method includes receiving child level information of the macro block including at least a location of a logic leaflet, receiving parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer, and selecting a pin location based on the child level information and the parent level information.

First claim

What is claimed is:

1. A computer implemented method for improving interior pinning in a macro block of an integrated circuit, the method comprising:
receiving child level information of the macro block including a logic leaflet in the integrated circuit and parent level information including edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer in the integrated circuit, wherein the logic leaflet defines a connecting point for a pin in the integrated circuit;
determining an ideal pin placement based on the logic leaflet in the integrated circuit, the ideal pin placement is directly above a logic leaflet location of the logic leaflet;
selecting, by a computer, a pin location of the pin in the integrated circuit for placing the pin in relation to the ideal pin placement, wherein the pin location selected is not the ideal pin placement, and wherein the pin location is selected when the ideal pin placement is unavailable; and
placing the pin at the pin location selected.

2. The computer implemented method of claim 1 , wherein determining the pin location to select for placing the pin in relation to the ideal pin placement comprises determining a nearest available pin slot in relation to the ideal pin placement.

3. The computer implemented method of claim 2 , wherein the nearest available pin slot is an empty slot with available routing resources between the slot and a macro edge that the pin to be placed requires, the empty slot is nearest the ideal pin placement.

4. The computer implemented method of claim 3 , further comprising selecting the nearest available pin slot as the pin location for the pin to be placed.

5. The computer implemented method of claim 1 , wherein determining the pin location to select for placing the pin in relation to the ideal pin placement comprises selecting the pin location that connects to a power rail configured to connect to both an east end and a west end of the macro block of the integrated circuit.

6. The computer implemented method of claim 1 , wherein determining the pin location to select for placing the pin in relation to the ideal pin placement comprises selecting the pin location that connects to a power rail configured to connect to an east end of the macro block of the integrated circuit.

7. The computer implemented method of claim 1 , wherein determining the pin location to select for placing the pin in relation to the ideal pin placement comprises selecting the pin location that connects to a power rail configured to connect to west end of the macro block of the integrated circuit.

8. The computer implemented method of claim 1 , further comprising computing placement of the pin in the pin location; and
computing wiring of the pin to a desired edge of the macro block.

9. The computer implemented method of claim 1 , further comprising tracking routing resource values of the child level information as pin assignments are made.

10. A system for improving interior pinning in a macro block of an integrated circuit, the system comprising:
a memory having computer readable instructions; and
a processor configured to execute the computer readable instructions, the computer readable instructions comprising:
receive child level information of the macro block including a logic leaflet in the integrated circuit and parent level information including edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer in the integrated circuit, wherein the logic leaflet defines a connecting point for a pin in the integrated circuit;
determine an ideal pin placement based on the logic leaflet in the integrated circuit, the ideal pin placement is directly above a logic leaflet location of the logic leaflet;
select, by the processor, a pin location of the pin in the integrated circuit for placing the pin in relation to the ideal pin placement, wherein the pin location selected is not the ideal pin placement, and wherein the pin location is selected when the ideal pin placement is unavailable; and
placing the pin at the pin location selected.

11. The system of claim 10 , wherein determining the pin location to select for placing the pin in relation to the ideal pin placement comprises determining a nearest available pin slot in relation to the ideal pin placement.

12. The system of claim 11 , wherein the nearest available pin slot is an empty slot with available routing resources between the slot and a macro edge that the pin to be placed requires, the empty slot is nearest the ideal pin placement.

13. The system of claim 12 , further comprising selecting the nearest available pin slot as the pin location for the pin to be placed.

14. The system of claim 10 , wherein determining the pin location to select for placing the pin in relation to the ideal pin placement comprises selecting the pin location that connects to a power rail configured to connect to both an east end and a west end of the macro block of the integrated circuit.

15. The system of claim 10 , wherein determining the pin location to select for placing the pin in relation to the ideal pin placement comprises selecting the pin location that connects to a power rail configured to connect to an east end of the macro block of the integrated circuit.

16. The system of claim 10 , wherein determining the pin location to select for placing the pin in relation to the ideal pin placement comprises selecting the pin location that connects to a power rail configured to connect to west end of the macro block of the integrated circuit.

17. The system of claim 10 , further comprising computing placement of the pin in the pin location; and
computing wiring of the pin to a desired edge of the macro block.

18. A computer program product for improving interior pinning in a macro block of an integrated circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:
receive child level information of the macro block including a logic leaflet in the integrated circuit and parent level information including edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer in the integrated circuit, wherein the logic leaflet defines a connecting point for a pin in the integrated circuit;
determining an ideal pin placement based on the logic leaflet in the integrated circuit, the ideal pin placement is directly above a logic leaflet location of the logic leaflet;
select, by the processor, a pin location of the pin in the integrated circuit for placing the pin in relation to the ideal pin placement, wherein the pin location selected is not the ideal pin placement, and wherein the pin location is selected when the ideal pin placement is unavailable.

Assignees

• IBM

Inventors

• Affeldt Matthew D
• Berry Christopher J
• Darden Randall J
• Ramji Shyam
• St Juste Eddy

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F2115/08

  Intellectual property [IP] blocks or IP cores · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• G06F17/5077 Primary

  Physics · mapped topic