Reactive serial resistance reduction for magnetoresistive random-access memory devices

Patent metadata

Field	Value
Publication number	US-12364164-B2
Application number	US-202218064261-A
Country	US
Kind code	B2
Filing date	Dec 10, 2022
Priority date	Dec 10, 2022
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

A semiconductor device that includes a substrate, a crystalline bottom electrode layer on an upper side of the semiconductor substrate, a conductive crystalline metal layer above the crystalline bottom electrode layer, and a conductive oxide layer above the conductive crystalline metal layer. The conductive oxide layer has a low resistance. The semiconductor device also includes a magnetic tunnel junction (MTJ) above the conductive crystalline metal layer, the MTJ including a tunnel barrier layer, a free layer on a first side of the tunnel barrier layer and a reference layer on a second side of the tunnel barrier layer opposite the first side.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate extending along a first axis to define a length, a second axis orthogonal to the first axis to define a width, and a third axis orthogonal to the first and second axes to define a height;
a crystalline bottom electrode layer on an upper side of the semiconductor substrate;
a conductive crystalline metal layer disposed above the crystalline bottom electrode layer;
a conductive oxide layer having a low resistance disposed above the conductive crystalline metal layer; and
a magnetic tunnel junction (MTJ) disposed above the conductive crystalline metal layer, the MTJ comprising a tunnel barrier layer, a free layer disposed on a first side of the tunnel barrier layer and a reference layer disposed on a second side of the tunnel barrier layer opposite the first side.

2. The semiconductor device of claim 1 , wherein the free layer comprises an ordered alloy.

3. The semiconductor device of claim 1 , wherein the reference layer comprises an ordered alloy.

4. The semiconductor device of claim 1 , wherein the crystalline bottom electrode layer is formed from an amorphous Ta(N) layer.

5. The semiconductor device of claim 1 , wherein the low resistance is a resistance area product (RA) of less than 0.5 Ohm μm 2 .

6. The semiconductor device of claim 1 , wherein the conductive crystalline metal layer is generated from annealing of an amorphous metal layer comprising CoFeB or ZrCo.

7. The semiconductor device of claim 1 , wherein the conductive oxide layer is a shunted MgO layer and further comprises a material selected from the list consisting of Lithium, Aluminum, Scandium and other rare earth metals.

8. The semiconductor device of claim 7 , wherein:
the conductive oxide layer comprises the other rare earth metal; and
the other rare earth metal is Gadolinium or Yttrium.

9. The semiconductor device of claim 1 , wherein the conductive oxide layer comprises one or more shunting paths and the conductive oxide layer has a thickness of 1.5 nm-3 nm.

10. The semiconductor device of claim 1 , wherein an ordered alloy forms the free layer and the reference layer comprises one or more interfacial layers, or spacers, and one or more other layers, each of the one or more other layers comprising a material selected from the list consisting of cobalt, platinum, palladium, ruthenium, tantalum, iron, boron, cobalt-platinum, or cobalt-palladium.

11. The semiconductor device of claim 1 , wherein an ordered alloy forms the reference layer and the free layer comprises CoFe.

12. The semiconductor device of claim 11 , wherein the ordered alloy is a Heusler alloy or a tetragonal material.

13. A method of fabricating the semiconductor device of claim 1 , comprising: depositing an amorphous bottom electrode layer on a semiconductor substrate; depositing a conductive amorphous metal layer on the amorphous bottom electrode layer; depositing an amorphous reactive material on the conductive amorphous metal layer; depositing an insulating oxide layer on the amorphous reactive template; depositing an ordered alloy structure comprising a free layer or a reference layer on the insulating oxide layer; depositing a tunnel barrier layer on the ordered alloy structure; and performing a stack annealing process on the semiconductor device, responsive to which the amorphous reactive material reacts with and shunts the insulating oxide layer to form a conductive oxide layer.

14. The method of claim 13 , wherein the ordered alloy structure further comprises a seed layer.

15. The method of claim 14 , further comprising:
depositing the seed layer on the insulating oxide layer prior to depositing the free layer or the reference layer on the seed layer.

16. The method of claim 15 , wherein:
the free layer is deposited on the seed layer; and
further comprising responsive to depositing the free layer on the seed layer and the tunnel barrier layer on the free layer:
depositing another conductive amorphous metal layer on the tunnel barrier layer;
depositing a synthetic antiferromagnetic (SAF) layer on the another conductive amorphous metal layer; and
depositing the reference layer on the SAF to provide a bottom free layer MTJ device.

17. The method of claim 15 , wherein:
the reference layer is deposited on the seed layer; and
further comprising responsive to depositing the reference layer on the seed layer and the tunnel barrier layer on the reference layer:
depositing the free layer on the tunnel barrier layer;
depositing an oxide cap layer on the free layer; and
depositing a top electrode layer on the oxide cap layer to provide a top free layer MTJ device.

18. The method of claim 13 , wherein the conductive amorphous metal layer is deposited as a CoFeB or ZrCo layer.

19. The method of claim 13 , wherein the amorphous reactive material is deposited as a material selected from the list comprising Lithium Boron alloy (LiB), Aluminum Boron alloy (AlB), Scandium Boron alloy (ScB), and other rare earth boron alloy.

20. The method of claim 13 , wherein the stack annealing process is performed at a temperature of 300-425° C.

Assignees

• IBM

Inventors

• Gottwald Matthias Georg
• Hu Guohan
• Brown Stephen L
• Reznicek Alexander

Classifications

• H01F10/3272

  by use of anti-parallel coupled [APC] ferromagnetic layers, e.g. artificial ferrimagnets [AFI], artificial [AAF] or synthetic [SAF] anti-ferromagnets · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title

• H10N50/80

  Constructional details · CPC title