Memory device

Patent metadata

Field	Value
Publication number	US-11837288-B2
Application number	US-202117470867-A
Country	US
Kind code	B2
Filing date	Sep 9, 2021
Priority date	Mar 12, 2021
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

According to one embodiment, a memory device includes: a memory cell including a memory element and a switching element; and a circuit that applies a first write pulse having a first polarity to the memory cell at the time of writing first data in the memory cell and applies a second write pulse having a second polarity different from the first polarity to the memory cell at the time of writing second data in the memory cell. The switching element has polarity dependence according to the first and second polarities.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell including a memory element and a switching element; and
a circuit that applies a first write pulse having a first polarity to the memory cell at the time of writing first data in the memory cell and applies a second write pulse having a second polarity different from the first polarity to the memory cell at the time of writing second data in the memory cell,
wherein
the switching element has polarity dependence according to the first and second polarities.

2. The memory device according to claim 1 , wherein
a first threshold voltage of the switching element when the first write pulse is applied is different from a second threshold voltage of the switching element when the second write pulse is applied.

3. The memory device according to claim 1 , wherein
when the first write pulse is indicated by “VwAPP”, the second write pulse is indicated by “VwPAP”, a ratio between the first and second write pulses is indicated by “a”, and the polarity dependence of the switching element is indicated by “b”, “a” has a relationship of Formula (1), and “b” has a relationship of Formula (2):
a =VwPAP/VwAPP  (1)

1< b<a 2   (2).

4. The memory device according to claim 3 , wherein
the “b” is equal to the “a”.

5. The memory device according to claim 1 , wherein
a first resistance value of the switching element when the first write pulse is applied is different from a second resistance value of the switching element when the second write pulse is applied.

6. The memory device according to claim 1 , wherein
the switching element includes a first electrode, a second electrode, and a first layer between the first electrode and the second electrode, and
a material of the first electrode is different from a material of the second electrode.

7. The memory device according to claim 1 , wherein
the polarity dependence of the switching element is set based on a condition for forming the switching element.

8. The memory device according to claim 1 , wherein
the memory element has polarity dependence according to the first and second polarities.

9. The memory device according to claim 1 , wherein
the memory element is a magnetoresistive effect element,
the magnetoresistive effect element includes:
a first magnetic layer having a variable magnetization direction;
a second magnetic layer having an invariable magnetization direction; and
an insulating layer between the first magnetic layer and the second magnetic layer, and
polarity dependence of the magnetoresistive effect element on the first and second write pulses is set by controlling at least one of a dimension of the first magnetic layer and a composition of a constituent element of the first magnetic layer.

10. A memory device comprising:
a memory cell including a memory element and a switching element; and
a circuit that applies a first write pulse having a first polarity to the memory cell at the time of writing first data in the memory cell and applies a second write pulse having a second polarity different from the first polarity to the memory cell at the time of writing second data in the memory cell,
wherein
a first resistance value of the switching element when the first write pulse is applied is different from a second resistance value of the switching element when the second write pulse is applied.

11. The memory device according to claim 10 , wherein
a first threshold voltage of the switching element when the first write pulse is applied is different from a second threshold voltage of the switching element when the second write pulse is applied.

12. The memory device according to claim 10 , wherein
the switching element has polarity dependence according to the first and second polarities.

13. The memory device according to claim 12 , wherein
when the first write pulse is indicated by “VwAPP”, the second write pulse is indicated by “VwPAP”, a ratio between the first and second write pulses is indicated by “a”, and the polarity dependence of the switching element is indicated by “b”, “a” has a relationship of Formula (1), and “b” has a relationship of Formula (2):
a =VwPAP/VwAPP  (1)

1< b<a 2   (2).

14. The memory device according to claim 13 , wherein
the “b” is equal to the “a”.

15. The memory device according to claim 10 , wherein
the switching element includes a first electrode, a second electrode, and a first layer between the first electrode and the second electrode, and
a material of the first electrode is different from a material of the second electrode.

16. The memory device according to claim 10 , wherein
a difference between the first resistance value and the second resistance value of the switching element is set based on a condition for forming the switching element.

17. The memory device according to claim 10 , wherein
the memory element has polarity dependence according to the first and second polarities.

18. The memory device according to claim 10 , wherein
the memory element is a magnetoresistive effect element,
the magnetoresistive effect element includes:
a first magnetic layer having a variable magnetization direction;
a second magnetic layer having an invariable magnetization direction; and
an insulating layer between the first magnetic layer and the second magnetic layer, and
polarity dependence of the magnetoresistive effect element on the first and second write pulses is set by controlling at least one of a dimension of the first magnetic layer and a composition of a constituent element of the first magnetic layer.

Assignees

• Kioxia Corp

Inventors

• Matsushita Naoki

Classifications

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C13/0028

  Word-line or row circuits · CPC title

• G11C13/0038

  Power supply circuits · CPC title