Stacked transistors having an isolation region therebetween and a common gate electrode, and related fabrication methods

Patent metadata

Field	Value
Publication number	US-12356665-B2
Application number	US-202117554483-A
Country	US
Kind code	B2
Filing date	Dec 17, 2021
Priority date	Sep 23, 2021
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

First claim

What is claimed is:

1. A transistor device comprising:
a substrate;
a lower transistor comprising a lower gate, a lower channel region on the substrate, lower insulating spacers on sidewalls of the lower gate, and a lower source/drain region;
an upper transistor comprising an upper gate, an upper channel region, upper insulating spacers on sidewalls of the upper gate, and an upper source/drain region, wherein the lower transistor is between the upper transistor and the substrate; and
an isolation region that separates the lower insulating spacers from the upper insulating spacers, the isolation region comprising a first portion that separates the lower channel region from the upper channel region and a second portion that separates the lower source/drain region from the upper source/drain region,
wherein the lower gate of the lower transistor contacts the upper gate of the upper transistor, and
wherein the first portion of the isolation region has a first thickness that is less than or equal to a second thickness of the second portion of the isolation region.

2. The transistor device of claim 1 , wherein a lower surface of the upper gate of the upper transistor contacts an upper surface of the lower gate of the lower transistor.

3. The transistor device of claim 1 ,
wherein the upper gate of the upper transistor is on opposite sidewalls of the isolation region, and
wherein the isolation region is thicker than the upper channel region of the upper transistor.

4. The transistor device of claim 1 ,
wherein the lower and upper transistors are lower and upper nanosheet transistors, respectively,
wherein the lower nanosheet transistor comprises a plurality of lower nanosheets, a first of which defines the lower channel region,
wherein the upper nanosheet transistor comprises a plurality of upper nanosheets, a first of which defines the upper channel region, and
wherein the first portion of the isolation region separates the plurality of lower nanosheets of the lower nanosheet transistor from the plurality of upper nanosheets of the upper nanosheet transistor.

5. The transistor device of claim 1 , wherein the first portion of the isolation region has a first thickness that is thinner than a second thickness of the second portion of the isolation region.

6. The transistor device of claim 1 ,
wherein one of the lower insulating spacers contacts a sidewall of the lower source/drain region and a lower portion of the isolation region, and
wherein one of the upper insulating spacers contacts a sidewall of the upper source/drain region and an upper portion of the isolation region.

7. The transistor device of claim 1 ,
wherein a first one of the lower transistor or the upper transistor comprises a gate-all-around (GAA) nanosheet transistor or a tri-gate nanosheet transistor, and
wherein a second one of the lower transistor or the upper transistor, different from the first one, comprises a vertical field-effect transistor (VFET) or a fin field-effect transistor (FinFET).

8. A transistor device comprising:
a lower nanosheet transistor comprising a lower nanosheet stack and a lower gate on the lower nanosheet stack;
an upper nanosheet transistor on top of the lower nanosheet transistor, the upper nanosheet transistor comprising an upper nanosheet stack and an upper gate on the upper nanosheet stack; and
an isolation region that separates the lower nanosheet stack from the upper nanosheet stack,
wherein the lower gate of the lower nanosheet transistor contacts the upper gate of the upper nanosheet transistor,
wherein the lower nanosheet transistor further comprises a lower insulating spacer that contacts a lower portion of the isolation region, and
wherein the upper nanosheet transistor further comprises an upper insulating spacer that contacts an upper portion of the isolation region.

9. The transistor device of claim 8 , wherein an upper surface of the lower gate of the lower nanosheet transistor contacts a lower surface of the upper gate of the upper nanosheet transistor.

10. The transistor device of claim 8 , wherein the upper gate of the upper nanosheet transistor contacts opposite sidewalls of the isolation region.

11. A method of forming a transistor device, the method comprising:
forming a preliminary transistor stack comprising a lower channel layer, an upper channel layer, and a sacrificial layer that separates the lower channel layer from the upper channel layer and overlaps the lower channel layer and the upper channel layer in a first direction;
forming insulating spacers between the lower channel layer and the upper channel layer;
removing the sacrificial layer;
forming an isolation layer in an opening that is formed by removing the sacrificial layer and overlaps the insulating spacers in the first direction; and
forming a lower gate on the lower channel layer below the isolation layer and an upper gate on the upper channel layer above the isolation layer.

12. The method of claim 11 , wherein the insulating spacers are formed before removing the sacrificial layer.

13. The method of claim 11 , wherein the insulating spacers are formed after removing the sacrificial layer and forming the isolation layer.

14. The method of claim 11 , wherein the preliminary transistor stack further comprises:
a plurality of lower nanosheets, a first of which defines the lower channel layer;
a plurality of lower sacrificial layers that alternate with the plurality of lower nanosheets;
a plurality of upper nanosheets, a first of which defines the upper channel layer; and
a plurality of upper sacrificial layers that alternate with the plurality of upper nanosheets.

15. The method of claim 14 , wherein forming the insulating spacers comprises:
forming lower ones of the insulating spacers on sidewalls of the plurality of lower sacrificial layers; and
forming upper ones of the insulating spacers on sidewalls of the plurality of upper sacrificial layers.

16. The method of claim 15 , wherein the upper ones of the insulating spacers are formed before the lower ones of the insulating spacers.

17. The method of claim 15 , wherein the upper ones of the insulating spacers are formed simultaneously with the lower ones of the insulating spacers.

18. The method of claim 14 ,
wherein the preliminary transistor stack further comprises a bottom sacrificial layer that is below the plurality of lower sacrificial layers,
wherein the bottom sacrificial layer is thinner than the sacrificial layer and thicker than each of the plurality of lower sacrificial layers,
wherein the method further comprises:
removing the bottom sacrificial layer;
forming a bottom isolation layer in an opening formed by removing the bottom sacrificial layer; and
removing the plurality of lower sacrificial layers and the plurality of upper sacrificial layers after forming the isolation layer and the bottom isolation layer,

wherein forming the lower gate comprises forming the lower gate in openings formed by removing the plurality of lower sacrificial layers, and
wherein forming the upper gate comprises forming the upper gate in openings formed by removing the plurality of upper sacrificial layers.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yun Seungchan
• Hwang Inchan
• Jo Gunho
• Yim Jeonghyuk
• Hong Byounghak
• Seo Kang-Ill
• He Ming
• Park Jaehyun
• Saremi Mehdi
• Park Rebecca
• Simka Harsono
• Ha Daewon

Classifications

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title