Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure

Patent metadata

Field	Value
Publication number	US-2020006331-A1
Application number	US-201816024080-A
Country	US
Kind code	A1
Filing date	Jun 29, 2018
Priority date	Jun 29, 2018
Publication date	Jan 2, 2020
Grant date	—

Abstract

A stacked transistor architecture has a fin structure that includes lower and upper portions separated by an isolation region built into the fin structure. Upper and lower gate structures on respective upper and lower fin structure portions may be different from one another (e.g., with respect to work function metal and/or gate dielectric thickness). One example methodology includes depositing lower gate structure materials on the lower and upper channel regions, recessing those materials to re-expose the upper channel region, and then re-depositing upper gate structure materials on the upper channel region. Another example methodology includes depositing a sacrificial protective layer on the upper channel region. The lower gate structure materials are then deposited on both the exposed lower channel region and sacrificial protective layer. The lower gate structure materials and sacrificial protective layer are then recessed to re-expose upper channel region so that upper gate structure materials can be deposited.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a fin structure including an upper portion having opposing sidewalls and a lower portion having opposing sidewalls, wherein the sidewalls of the upper portion are collinear with the sidewalls of the lower portion; a first gate structure on the upper portion, the first gate structure including a first gate electrode and a first gate dielectric between the first gate electrode and the upper portion; and a second gate structure on the lower portion, the second gate structure including a second gate electrode and a second gate dielectric between the second gate electrode and the lower portion; wherein the first gate structure is different from the second gate structure with respect to at least one of composition and gate dielectric thickness.

2 . The integrated circuit structure of claim 1 , wherein the first gate electrode includes a first metal and the second gate electrode includes a second metal that is compositionally different from the first metal.

3 . The integrated circuit structure of claim 1 , wherein the first gate dielectric has a first thickness and the second gate dielectric has a second thickness that is at least 0.5 nm different from the first thickness.

4 . The integrated circuit structure of claim 3 , wherein the second thickness is at least 1 nm different from the first thickness.

5 . The integrated circuit structure of claim 1 , wherein the fin structure further includes an isolation region between the upper and lower portions, the isolation region configured to provide electrical isolation between the upper and lower portions.

6 . The integrated circuit structure of claim 5 , wherein the isolation region comprises insulator material.

7 . The integrated circuit structure of claim 5 , wherein the isolation region comprises doping or fixed charge isolation.

8 . The integrated circuit structure of claim 5 , wherein the isolation region is within at least one of the upper and lower portions.

9 . The integrated circuit structure of claim 5 , wherein the first gate dielectric is also between the isolation region and the gate electrode.

10 . The integrated circuit structure of claim 1 , wherein at least one of the first and second gate dielectrics comprises a high-k dielectric.

11 . The integrated circuit structure of claim 1 , wherein at least one of the first and second gate dielectrics has a thickness in the range of 5 angstroms to 2 nm.

12 . The integrated circuit structure of claim 1 , further comprising:
a first source region and a first drain region adjacent the first gate structure; and a second source region and a second drain region adjacent the second gate structure.

13 . The integrated circuit structure of claim 1 , wherein the upper portion includes one or more nanowires or nanoribbons, and the first gate structure wraps around the upper portion, and the sidewalls of the upper portion include sidewalls of the one or more nanowires or nanoribbons.

14 . The integrated circuit structure of claim 1 , wherein the lower portion includes one or more nanowires or nanoribbons, and the second gate structure wraps around the lower portion, and the sidewalls of the lower portion include sidewalls of the one or more nanowires or nanoribbons.

15 . The integrated circuit structure of claim 1 , wherein the upper portion includes a fin, and the first gate structure is on opposing sidewalls and a top of the upper portion, and the sidewalls of the upper portion include the sidewalls of the fin.

16 . The integrated circuit structure of claim 1 , wherein the lower portion includes a fin, and the second gate structure is on opposing sidewalls of the lower portion, and the sidewalls of the lower portion include the sidewalls of the fin.

17 . The integrated circuit structure of claim 1 , wherein the integrated circuit structure is part of a processor or communications chip.

18 . The integrated circuit structure of claim 1 , wherein the integrated circuit structure is part of a mobile communications device.

19 . An integrated circuit structure, comprising:
a fin structure including an upper portion in the form of a fin, nanowire, or nanoribbon and a lower portion in the form of a fin, nanowire, or nanoribbon, wherein sidewalls of the upper portion are collinear with sidewalls of the lower portion; a first gate structure at least on the sidewalls of the upper portion, the first gate structure including a first gate electrode and a first gate dielectric, the first gate dielectric between the first gate electrode of the upper portion, the first gate electrode including a first metal, and the first gate dielectric having a first thickness; a first source region and a first drain region adjacent the first gate structure; a second gate structure on the sidewalls of the lower portion, the second gate structure including a second gate electrode and a second gate dielectric, the second gate dielectric between the second gate electrode and the lower portion, the second gate electrode including a second metal that is compositionally different from the first metal, and the second gate dielectric having a second thickness that is at least 1 nm different from the first thickness; and a second source region and a second drain region adjacent the second gate structure.

20 . The integrated circuit structure of claim 19 , wherein the fin structure further includes an isolation region between the upper and lower portions, the isolation region comprising an insulator material or a dopant, and the first gate dielectric is also between the isolation region and the gate electrode.

Assignees

• Intel Corp

Inventors

• Lilak Aaron D
• Dewey Gilbert
• Rachmady Willy
• Hourani Rami
• Bojarski Stephanie A
• Mehandru Rishabh
• Phan Anh
• Mannebach Ehren

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L27/0886 Primary

  Electricity · mapped topic

• H01L29/7855

  Electricity · mapped topic

• H01L29/42356

  Electricity · mapped topic

• H01L29/1033

  Electricity · mapped topic