Hyperchip

Patent metadata

Field	Value
Publication number	US-12355002-B2
Application number	US-202418615654-A
Country	US
Kind code	B2
Filing date	Mar 25, 2024
Priority date	Dec 29, 2016
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

First claim

What is claimed is:

1. An integrated circuit assembly, comprising:
a first integrated circuit chip comprising:
a bulk silicon substrate;
transistor devices on the bulk silicon substrate;
a first group of interconnect levels on the transistor devices;
a second group of interconnect levels on the first group of interconnect levels; and
through silicon vias in the bulk silicon substrate and in the first group of interconnect levels but not in the second group of interconnect levels, wherein the second group of interconnect levels covers the through silicon vias; and

a second integrated circuit chip mounted on the first integrated circuit chip, the second integrated circuit chip having an area smaller than and within an area of the first integrated circuit chip, and the second integrated circuit chip electrically coupled to the through silicon vias of the first integrated circuit chip.

2. The integrated circuit assembly of claim 1 , wherein the second integrated circuit chip has a device side facing the first integrated circuit chip.

3. The integrated circuit assembly of claim 1 , wherein the first integrated circuit chip has a device side facing the second integrated circuit chip.

4. The integrated circuit assembly of claim 1 , further comprising:
a first silicon die coupled to the first integrated circuit chip, the first silicon die laterally spaced apart from the second integrated circuit chip; and
a second silicon die coupled to the first integrated circuit chip, the second silicon die laterally spaced apart from the second integrated circuit chip.

5. The integrated circuit assembly of claim 4 , wherein the first silicon die is a third integrated circuit chip, and the second silicon die is a fourth integrated circuit chip.

6. The integrated circuit assembly of claim 1 , wherein the second integrated circuit chip is electrically coupled to the through silicon vias of the first integrated circuit chip.

7. The integrated circuit assembly of claim 1 , further comprising:
a heat sink over the second integrated circuit chip.

8. The integrated circuit assembly of claim 1 , further comprising:
a package substrate, wherein the first integrated circuit chip is coupled to the package substrate.

9. A system, comprising:
a package substrate;
a first integrated circuit chip coupled to the package substrate, the first integrated circuit chip comprising:
a bulk silicon substrate;
transistor devices on the bulk silicon substrate;
a first group of interconnect levels on the transistor devices;
a second group of interconnect levels on the first group of interconnect levels; and
through silicon vias in the bulk silicon substrate and in the first group of interconnect levels but not in the second group of interconnect levels, wherein the second group of interconnect levels covers the through silicon vias;

a second integrated circuit chip mounted on the first integrated circuit chip, the second integrated circuit chip having an area smaller than and within an area of the first integrated circuit chip, and the second integrated circuit chip electrically coupled to the through silicon vias of the first integrated circuit chip; and
a plurality of solder balls on a side of the package substrate opposite the first integrated circuit chip.

10. The system of claim 9 , further comprising:
a heat sink above the second integrated circuit chip.

11. The system of claim 9 , wherein the footprint of the second integrated circuit chip is smaller than the footprint of the first integrated circuit chip.

12. The system of claim 9 , further comprising:
a third integrated circuit chip on the first integrated circuit chip in a device side to device side configuration.

13. The system of claim 12 , further comprising:
a fourth integrated circuit chip on the first integrated circuit chip in a device side to device side configuration.

14. The system of claim 9 , wherein the second integrated circuit chip is a multi-core die.

15. The system of claim 9 , wherein the second integrated circuit chip is a graphics die.

16. The system of claim 9 , wherein the second integrated circuit chip has a device side facing the first integrated circuit chip.

17. An integrated circuit assembly, comprising:
a first integrated circuit chip comprising:
a bulk silicon substrate;
transistor devices on the bulk silicon substrate;
a first group of interconnect levels on the transistor devices;
a second group of interconnect levels on the first group of interconnect levels; and
through silicon vias in the bulk silicon substrate and in the first group of interconnect levels but not in the second group of interconnect levels, wherein the second group of interconnect levels covers the through silicon vias;

a second integrated circuit chip mounted on the first integrated circuit chip, the second integrated circuit chip having a footprint within the footprint of the first integrated circuit chip;
a first silicon die coupled to the first integrated circuit chip, the first silicon die laterally spaced apart from the second integrated circuit chip;
a second silicon die coupled to the first integrated circuit chip, the second silicon die laterally spaced apart from the second integrated circuit chip;
a heat sink over the second integrated circuit chip, over the first silicon die, and over the second silicon die; and
a package substrate, wherein the first integrated circuit chip is coupled to the package substrate.

18. The integrated circuit assembly of claim 17 , wherein the second integrated circuit chip is electrically coupled to the through silicon vias of the first integrated circuit chip.

19. The integrated circuit assembly of claim 17 , wherein the first silicon die is a third integrated circuit chip, and the second silicon die is a fourth integrated circuit chip.

20. The integrated circuit assembly of claim 17 , wherein the second integrated circuit chip has a device side facing the first integrated circuit chip.

Assignees

• Intel Corp

Inventors

• Bohr Mark T
• Gomes Wilfred
• Kumar Rajesh
• Tadayon Pooya
• Ingerly Doug

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title