Hyperchip

Patent metadata

Field	Value
Publication number	US-11024601-B2
Application number	US-201716348448-A
Country	US
Kind code	B2
Filing date	Dec 21, 2017
Priority date	Dec 29, 2016
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

First claim

What is claimed is:

1. An integrated circuit assembly, comprising:
a first integrated circuit chip comprising a device side opposite a backside, the device side comprising a plurality of transistor devices and a plurality of device contact points, and the backside comprising a plurality of backside contacts;
a second integrated circuit chip comprising a device side comprising a plurality of device contact points thereon, the second integrated circuit chip on the first integrated circuit chip in a device side to device side configuration, wherein ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip, and wherein the second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective; and
a third integrated circuit chip comprising a device side comprising a plurality of device contact points thereon, the third integrated circuit chip on the first integrated circuit chip in a device side to device side configuration, wherein ones of the plurality of device contact points of the third integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip, and wherein the third integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective, wherein the plurality of transistor devices of the device side of the first integrated circuit chip comprises a plurality of transistor repeaters that routes communication signals between the second integrated circuit chip and the third integrated circuit chip.

2. The integrated circuit assembly of claim 1 , further comprising:
one or more additional integrated circuit chips, each of the one or more additional integrated circuit chips comprising a device side comprising a plurality of device contact points thereon, and each of the one or more additional integrated circuit chips on the first integrated circuit chip in a device side to device side configuration, wherein ones of the plurality of device contact points of each of the one or more additional integrated circuit chips are coupled to ones of the plurality of device contact points of the first integrated circuit chip, and wherein each of the one or more additional integrated circuit chips is smaller than the first integrated circuit chip from a plan view perspective.

3. The integrated circuit assembly of claim 2 , wherein at least one of the one or more additional integrated circuit chips comprises a different functionality than a functionality of the second integrated circuit chip.

4. The integrated circuit assembly of claim 1 , wherein the first integrated circuit chip comprises one or more through silicon vias (TSVs) extending between the device side and the backside, the one or more TSVs electrically coupled to the backside contacts.

5. The integrated circuit assembly of claim 4 , wherein the backside contacts comprise solder bumps.

6. The integrated circuit assembly of claim 4 , wherein the one or more TSVs are at least partially surrounded by a dielectric material.

7. The integrated circuit assembly of claim 1 , wherein a subset of the device contact points of the first integrated circuit chip are located in depopulated regions and have a larger diameter than others of the device contact points of the first integrated circuit chip.

8. The integrated circuit assembly of claim 7 , wherein the plurality of device contact points of the second integrated circuit chip have a same pattern as the device contact points of the first integrated circuit chip.

9. A packaged system, comprising:
a package substrate having die side contacts;
an integrated circuit assembly coupled to the package substrate, the integrated circuit assembly comprising:
a first integrated circuit chip comprising a device side opposite a backside, the device side comprising a plurality of transistor devices and a plurality of device contact points, and the backside comprising a plurality of backside contacts electrically coupled to the die side contacts of the package substrate; and
a second integrated circuit chip comprising a device side and a backside, the device side comprising a plurality of device contact points thereon, the second integrated circuit chip on the first integrated circuit chip in a device side to device side configuration, wherein ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip, and wherein the second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective;
a third integrated circuit chip comprising a device side and a backside, the device side comprising a plurality of device contact points thereon, the third integrated circuit chip on the first integrated circuit chip in a device side to device side configuration, wherein ones of the plurality of device contact points of the third integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip, and wherein the third integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective, wherein the plurality of transistor devices of the device side of the first integrated circuit chip comprises a plurality of transistor repeaters that routes communication signals between the second integrated circuit chip and the third integrated circuit chip; and
a heat sink coupled to the backside of the second integrated circuit chip and to a backside of the third integrated circuit chip.

10. The packaged system of claim 9 , wherein the integrated circuit assembly further comprises one or more additional integrated circuit chips, each of the one or more additional integrated circuit chips comprising a device side comprising a plurality of device contact points thereon, and each of the one or more additional integrated circuit chips on the first integrated circuit chip in a device side to device side configuration, wherein ones of the plurality of device contact points of each of the one or more additional integrated circuit chips are coupled to ones of the plurality of device contact points of the first integrated circuit chip, and wherein each of the one or more additional integrated circuit chips is smaller than the first integrated circuit chip from a plan view perspective.

11. The packaged system of claim 10 , wherein at least one of the one or more additional integrated circuit chips comprises a different functionality than a functionality of the second integrated circuit chip.

12. The packaged system of claim 9 , wherein the first integrated circuit chip of the integrated circuit assembly comprises one or more through silicon vias (TSVs) extending between the device side and the backside, the one or more TSVs electrically coupled to the backside contacts.

13. The packaged system of claim 12 , wherein the backside contacts comprise solder bumps.

14. The packaged system of claim 12 , wherein the one or more TSVs are at least partially surrounded by a dielectric material.

15. The packaged system of claim 9 , wherein a subset of the device contact points of the first integrated circuit chip of the integrated circuit assembly are located in depopulated regions and have a larger diameter than others of the device contact points of the first integrated circuit chip.

16. The packaged system of claim 15 , wherein the plurality of device contact points of the second

Assignees

• Intel Corp

Inventors

• Bohr Mark T
• Gomes Wilfred
• Kumar Rajesh
• Tadayon Pooya
• Ingerly Doug

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title