Omni directional interconnect with magnetic fillers in mold matrix

US12354883B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12354883-B2
Application numberUS-202117484315-A
CountryUS
Kind codeB2
Filing dateSep 24, 2021
Priority dateSep 24, 2021
Publication dateJul 8, 2025
Grant dateJul 8, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor interconnect assembly comprising: a mold layer having a first side and a second side, the mold layer comprising a mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material includes magnetic particles; a die embedded in the mold layer; one or more pillars extending in the mold layer from the first side to the second side; and wherein the second filler material is more densely dispersed within the mold layer along a gradient between the first side and the second side. 2. The assembly of claim 1 , wherein the second filler material comprises nickel, cobalt iron, nickel iron, or combinations thereof. 3. The assembly of claim 1 , wherein the second filler material comprises particles having an average diameter of about less than one micron each. 4. The assembly of claim 1 , wherein the second filler material is heterogeneously dispersed within the mold layer. 5. The assembly of claim 1 , wherein the die comprises an interconnect bridge die. 6. The assembly of claim 5 , wherein the interconnect bridge die comprises one or more through die vias for communication from a top side to a bottom side of the interconnect bridge. 7. The assembly of claim 1 , wherein the pillars comprise power delivery pillars, data transmission pillars, or an inductor. 8. The assembly of claim 1 , wherein the second filler material is densely dispersed within the mold layer adjacent the one or more pillars. 9. The assembly of claim 1 , further comprising one or more vias extending in the mold layer from the first side to the second side, each of the one or more vias filled with the second filler material. 10. The assembly of claim 1 , wherein the one or more pillars comprise the second filler material. 11. The assembly of claim 1 , further comprising one or more low filler areas with a lesser density of the second filler material compared to one or more high filler areas; and one or more vias extending in the mold layer from the first side to the second side, the one or more vias located in the one or more low filler areas. 12. A semiconductor assembly comprising: a layer having a first side and a second side, the layer comprising: a resin material; magnetic particles dispersed in the resin material; and dielectric particles dispersed in the resin material; a bridge die embedded in the layer; one or more pillars extending in the layer from the first side to the second side; and a ferromagnetic layer on the one or more pillars, wherein the magnetic particles are more densely dispersed within the layer adjacent the one or more pillars. 13. The assembly of claim 12 , wherein the one or more pillars each comprise copper pillars. 14. The assembly of claim 12 , wherein the one or more pillars each comprise power delivery pillars. 15. A semiconductor assembly comprising: a mold layer having a first side and a second side, the mold layer comprising a mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material includes magnetic particles; one or more low filler areas with a lesser density of the second filler material compared to one or more high filler areas; a bridge die embedded in the mold layer; one or more power delivery pillars extending in the mold layer from the first side to the second side; and one or more vias extending in the mold layer from the first side to the second side, the one or more vias located in the one or more low filler areas. 16. The assembly of claim 15 , wherein the second filler material comprises a thermally conductive material. 17. The assembly of claim 16 , wherein the magnetic particles comprise silver, aluminum, graphite, graphene, diamond, or combinations thereof. 18. The assembly of claim 15 , wherein the mold material further comprises a liquid metal, stress absorber material, dielectric material, or combinations thereof.

Assignees

Inventors

Classifications

  • Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

  • Fillings including materials for absorbing or reacting with moisture or other undesired substances · CPC title

  • Solid or gel fillings · CPC title

  • H10W74/473Primary

    containing a filler · CPC title

  • using moulds · CPC title

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Frequently asked questions

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What does patent US12354883B2 cover?
Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W74/473. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 08 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).