Microelectronic assemblies having magnetic core inductors

Patent metadata

Field	Value
Publication number	US-2020098621-A1
Application number	US-201816140398-A
Country	US
Kind code	A1
Filing date	Sep 24, 2018
Priority date	Sep 24, 2018
Publication date	Mar 26, 2020
Grant date	—

Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a first surface and an opposing second surface, wherein the first die is in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, wherein the magnetic core inductor may include a first conductive pillar at least partially surrounded by a magnetic material, and a second conductive pillar coupled to the first conductive pillar; and a second die having a first surface and an opposing second surface, wherein the second die is in a second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the magnetic core inductor.

First claim

1 . A microelectronic assembly, comprising:
a first die having a first surface and an opposing second surface in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, wherein the magnetic core inductor includes:
a first conductive pillar at least partially surrounded by a magnetic material; and
a second conductive pillar coupled to the first conductive pillar; and
a second die having a first surface and an opposing second surface, in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the magnetic core inductor.

2 . The microelectronic assembly of claim 1 , wherein the second conductive pillar of the magnetic core inductor is at least partially surrounded by the magnetic material.

3 . The microelectronic assembly of claim 1 , wherein the second conductive pillar is coupled to the first conductive pillar at the first surface of the magnetic core inductor.

4 . The microelectronic assembly of claim 1 , wherein the first surface of the magnetic core inductor is coupled to a package substrate.

5 . The microelectronic assembly of claim 4 , wherein the second conductive pillar is coupled to the first conductive pillar via a conductive pathway in the package substrate.

6 . The microelectronic assembly of claim 1 , wherein the first conductive pillar and the second conductive pillar are embedded in a magnetic material.

7 . The microelectronic assembly of claim 6 , wherein the magnetic material comprises one or more of: iron, nickel, cobalt, ferrite, a Heusler alloy, a permalloy, a Mu metal, a cobalt-zirconium-tantalum alloy, and a dielectric with magnetic particles or flakes.

8 . A microelectronic assembly, comprising:
a magnetic core inductor having a first surface and an opposing second surface in a first dielectric layer, wherein the magnetic core inductor includes a first conductive pillar at least partially surrounded by a magnetic material and a second conductive pillar coupled to the first conductive pillar; and a die having a first surface and an opposing second surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the first surface of the die is coupled to the second surface of the magnetic core inductor.

9 . The microelectronic assembly of claim 8 , wherein the second conductive pillar is coupled to the first conductive pillar at the first surface of the magnetic core inductor.

10 . The microelectronic assembly of claim 8 , further comprising:
a package substrate, and wherein the first surface of the magnetic core inductor is coupled to the package substrate.

11 . The microelectronic assembly of claim 10 , wherein the second conductive pillar is coupled to the first conductive pillar via a conductive pathway in the package substrate.

12 . The microelectronic assembly of claim 8 , wherein the magnetic material comprises one or more of: iron, nickel, cobalt, ferrite, a Heusler alloy, a permalloy, a Mu metal, a cobalt-zirconium-tantalum alloy, and a dielectric with magnetic particles or flakes.

13 . The microelectronic assembly of claim 8 , further comprising:
a redistribution layer at the first surface of the magnetic core inductor.

14 . The microelectronic assembly of claim 8 , further comprising:
a redistribution layer at the second surface of the magnetic core inductor.

15 . The microelectronic assembly of claim 8 , wherein a height of the first conductive pillar is between 50 microns and 500 microns.

16 . The microelectronic assembly of claim 8 , wherein the first conductive pillar includes copper.

17 . A method of manufacturing a microelectronic assembly, comprising:
forming a first conductive pillar in a first dielectric layer having a first surface and an opposing second surface; forming a second conductive pillar in the first dielectric layer having a first surface and an opposing second surface; forming a magnetic material at least partially around the first conductive pillar; forming a first interconnect between the first conductive pillar and a die at the second surface; forming a second interconnect between the second conductive pillar and the die at the second surface; and forming a conductive pathway between the first surface of the first conductive pillar and the first surface of the second conductive pillar.

18 . The method of claim 17 , wherein the conductive pathway is in a package substrate.

19 . The method of claim 17 , further comprising:
embedding the die in a second dielectric layer.

20 . The method of claim 17 , further comprising:
forming a redistribution layer at the first surface of the first and second conductive pillars, wherein the conductive pathway between the first surface of the first conductive pillar and the first surface of the second conductive pillar is in the redistribution layer.

21 . A computing device, comprising:
a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface in a first dielectric layer, and wherein the first surface of the first die is coupled to the second surface of the package substrate; an inductor having a first surface and an opposing second surface, wherein the inductor is in the first dielectric layer, wherein the inductor includes a first conductive pillar and a second conductive pillar coupled to the first conductive pillar, and wherein the first conductive pillar and the second conductive pillar are at least partially surrounded by a magnetic material; and a second die having a first surface and an opposing second surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the inductor and to the second surface of the first die.

22 . The computing device of claim 21 , wherein the first conductive pillar and the second conductive pillar are embedded in the magnetic material.

23 . The computing device of claim 21 , wherein the second conductive pillar is coupled to the first conductive pillar at the first surface of the inductor.

24 . The computing device of claim 21 , wherein the second conductive pillar is coupled to the first conductive pillar via a conductive pathway in the package substrate.

25 . The computing device of claim 21 , wherein the first die or the second die is a central processing unit, a radio frequency chip, a power converter, or a network processor.

Assignees

• Intel Corp

Inventors

• Bharath Krishna
• Elsherbini Adel A
• Liff Shawna M
• Radhakrishnan Kaladhar
• Qian Zhiguo
• Swan Johanna M

Classifications

• H10W20/098

  by filling between adjacent conductive parts · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title