Substrate inspection apparatus and substrate inspection method

Patent metadata

Field	Value
Publication number	US-12352808-B2
Application number	US-202318203138-A
Country	US
Kind code	B2
Filing date	May 30, 2023
Priority date	Nov 23, 2022
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

In a substrate inspection method, a substrate is provided on a substrate stage, the substrate having internal wires and connection wires, the internal wires respectively provided between stacked insulating layers, the connection wires respectively extending from the internal wires and exposed to an upper surface of the substrate. An electric circuit of the internal wires in the substrate is modeled to generate a circuit model. AC power is applied to the substrate stage to obtain measured capacitance values of the internal wires through currents that are obtained from the connection wires. DC power is applied to the substrate stage to obtain measured resistance values of the internal wires through voltages that are obtained from the connection wires. Impedance values of the internal wires are calculated through the measured capacitance values and the measured resistance values. The impedance values and the circuit model are compared to determine reliability of the substrate.

First claim

What is claimed is:

1. A substrate inspection method, the method comprising:
providing a substrate on a substrate stage, the substrate having a plurality of internal wires and a plurality of connection wires, the plurality of internal wires respectively provided between a plurality of insulating layers stacked on one another, the plurality of connection wires respectively extending from the plurality of the internal wires and exposed to an upper surface of the substrate;
modeling an electric circuit of the plurality of internal wires in the substrate to generate a circuit model;
applying AC power to the substrate stage to obtain measured capacitance values of the plurality of internal wires through currents that are obtained from the connection wires;
applying DC power to the substrate stage to obtain measured resistance values of the plurality of internal wires through voltages that are obtained from the connection wires;
calculating impedance values of the plurality of internal wires through the measured capacitance values and the measured resistance values; and
comparing the impedance values and the circuit model to determine reliability of the substrate.

2. The method of claim 1 , wherein modeling the electric circuit includes:
calculating basic capacitance values between internal wires that are provided adjacent to each other, wherein:
each basic capacitance value is defined by Equation 1:

C
0

=

ϵ
1

⁢

A

d
1

,

[

Equation
⁢

1

]

ϵ 1 is a first permittivity of a respective insulating layer,
d 1 is a thickness of the respective insulating layer, and
A is an area of an internal wire.

3. The method of claim 2 , wherein modeling the electric circuit includes:
calculating first theoretical capacitance values of the plurality of internal wires according to heights, wherein:
each first theoretical capacitance value is defined by Equation 2:

C
n

=

C
0

n

,

[

Equation
⁢

2

]

C 0 is the basic capacitance value, and
n is the number of layers between the substrate and a respective one of the plurality of internal wires.

4. The method of claim 1 , wherein modeling the electric circuit includes assuming that other circuit patterns provided outside the plurality of insulating layers in the substrate are equal potential with each other.

5. The method of claim 1 , wherein the substrate includes a through channel that has a conductive structure penetrating at least a portion of the plurality of insulating layers and an insulating structure covering an outer surface of the conductive structure.

6. The method of claim 5 , wherein modeling the electric circuit further includes:
calculating second theoretical capacitance values between the conductive structure and each of the plurality of internal wires, wherein:
each second theoretical capacitance value is defined by Equation 3:

C
CHH

=

2
⁢

πϵ
2

⁢
h

ln
(

1
+

r

r
-

d
2

)

,

[

Equation
⁢

3

]

ϵ2 is a second permittivity of the insulating structure,
h is a height of a respective internal wire,
r is a radius of the through channel, and
d2 is a second thickness of the insulating structure.

7. The method of claim 1 , wherein applying the AC power to the substrate stage to obtain the measured capacitance values of the plurality of internal wires includes:
obtaining the measured capacitance values through Equation 4:

C
=

i

2
⁢
π
⁢

f
⁢
V

,

[

Equation
⁢

4

]

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Sekye
• Lee Jinwoo
• Sun Jongcheon
• Lee Suyoung
• Lee Hyeongcheol
• Jun Chungsam

Classifications

• G01R27/02

  Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant (by measuring phase angle only G01R25/00) · CPC title

• G01R27/2605

  Measuring capacitance (capacitive sensors G01D5/24) · CPC title

• G01R31/287 Primary

  Procedures; Software aspects · CPC title

• G01R27/2617

  Measuring dielectric properties, e.g. constants (testing dielectric strength G01R31/12; detecting insulation faults G01R31/52; G01R27/2688 takes precedence) · CPC title

• G01R31/2853 Primary

  Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66) · CPC title