Substrate-less silicon controlled rectifier (SCR) integrated circuit structures

Patent metadata

Field	Value
Publication number	US-12328947-B2
Application number	US-202117357754-A
Country	US
Kind code	B2
Filing date	Jun 24, 2021
Priority date	Jun 24, 2021
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.

First claim

What is claimed is:

1. A substrate-less integrated circuit structure, comprising:
a first fin portion and a second fin portion that meet at a junction;
a plurality of gate structures over the first fin portion and the second fin portion; and
a plurality of P-type epitaxial structures and N-type epitaxial structures between corresponding adjacent ones of the plurality of gate structures, wherein pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures, and a corresponding one or more open locations is between neighboring pairs of the P-type epitaxial structures and pairs of the N-type epitaxial structures, wherein each of the one or more open locations is directly between corresponding ones of the plurality of gate structures.

2. The substrate-less integrated circuit structure of claim 1 , wherein the first fin portion includes P-well doping, and the second fin portion includes N-well doping.

3. The substrate-less integrated circuit structure of claim 1 , wherein the substrate-less integrated circuit structure is a silicon controlled rectifier (SCR).

4. The substrate-less integrated circuit structure of claim 1 , wherein the P-type epitaxial structures are boron-doped silicon or boron-doped silicon germanium structures.

5. The substrate-less integrated circuit structure of claim 1 , wherein the N-type epitaxial structures are phosphorous-doped silicon structures.

6. A computing device, comprising:
a board; and
a component coupled to the board, the component including a substrate-less integrated circuit structure, comprising:
a first fin portion and a second fin portion that meet at a junction;
a plurality of gate structures over the first fin portion and the second fin portion; and
a plurality of P-type epitaxial structures and N-type epitaxial structures between corresponding adjacent ones of the plurality of gate structures, wherein pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures, and a corresponding one or more open locations is between neighboring pairs of the P-type epitaxial structures and pairs of the N-type epitaxial structures, wherein each of the one or more open locations is directly between corresponding ones of the plurality of gate structures.

7. The computing device of claim 6 , further comprising:
a memory coupled to the board.

8. The computing device of claim 6 , further comprising:
a communication chip coupled to the board.

9. The computing device of claim 6 , wherein the component is a packaged integrated circuit die.

10. The computing device of claim 6 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

11. A substrate-less integrated circuit structure, comprising:
a first fin portion and a second fin portion that meet at a junction;
a plurality of gate structures over the first fin portion and the second fin portion;
a plurality of P-type epitaxial structures and N-type epitaxial structures between corresponding adjacent ones of the plurality of gate structures, wherein a pair of the P-type epitaxial structures is over the second fin portion, and a pair of the N-type epitaxial structures is over the first fin portion;
an open location over the junction between the first fin portion and the second fin portion, wherein the open location is directly between corresponding ones of the plurality of gate structures;
a first backside metallization structure coupled to a bottom of the first fin portion; and
a second backside metallization structure coupled to a bottom of the second fin portion.

12. The substrate-less integrated circuit structure of claim 11 , wherein the first fin portion includes P-well doping, and the second fin portion includes N-well doping.

13. The substrate-less integrated circuit structure of claim 11 , wherein the substrate-less integrated circuit structure is a silicon controlled rectifier (SCR).

14. The substrate-less integrated circuit structure of claim 11 , wherein the P-type epitaxial structures are boron-doped silicon or boron-doped silicon germanium structures.

15. The substrate-less integrated circuit structure of claim 11 , wherein the N-type epitaxial structures are phosphorous-doped silicon structures.

16. A computing device, comprising:
a board; and
a component coupled to the board, the component including a substrate-less integrated circuit structure, comprising:
a first fin portion and a second fin portion that meet at a junction;
a plurality of gate structures over the first fin portion and the second fin portion;
a plurality of P-type epitaxial structures and N-type epitaxial structures between corresponding adjacent ones of the plurality of gate structures, wherein a pair of the P-type epitaxial structures is over the second fin portion, and a pair of the N-type epitaxial structures is over the first fin portion;
an open location over the junction between the first fin portion and the second fin portion, wherein the open location is directly between corresponding ones of the plurality of gate structures;
a first backside metallization structure coupled to a bottom of the first fin portion; and
a second backside metallization structure coupled to a bottom of the second fin portion of the P-type epitaxial structures and pairs of the N-type epitaxial structures.

17. The computing device of claim 16 , further comprising:
a memory coupled to the board.

18. The computing device of claim 16 , further comprising:
a communication chip coupled to the board.

19. The computing device of claim 16 , wherein the component is a packaged integrated circuit die.

20. The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• Ma Rui
• Kolluru Kalyan
• THOMSON Nicholas
• Kar Ayan
• Orr Benjamin
• Jack Nathan
• Guha Biswajeet
• Greene Brian
• Lin Chung-Hsun

Classifications

• H10D84/80

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) · CPC title

• H10D18/251

  Lateral thyristors · CPC title

• H10D64/291

  Gate electrodes for thyristors · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title