Semiconductor apparatus and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12317612-B2
Application number	US-202017620253-A
Country	US
Kind code	B2
Filing date	Jun 26, 2020
Priority date	Jun 26, 2019
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

An apparatus and method enabling a reduction in a resistance of a conductive path electrically connecting an upper substrate and a lower substrate. The apparatus includes a first semiconductor layer with element formation regions disposed adjacent to one another via element isolation regions, each of the element formation regions having a first active element, contact regions on an element isolation region side of a front layer portion of the element formation regions, conductive pads connected to the contact regions and extending across the element isolation region, a first insulating layer, a second semiconductor layer on the first insulating layer and having a second active element, a second insulating layer covering the second semiconductor layer, and conductive plugs extending from the second insulating layer to the conductive pad, the conductive plugs including a material identical to a material of the conductive pad and formed integrally with the conductive pad.

First claim

What is claimed is:

1. A semiconductor apparatus, comprising:
a first semiconductor layer including a plurality of element formation regions disposed adjacent to one another via element isolation regions, each of the plurality of element formation regions being provided with a first active element;
contact regions each provided on a side of the element isolation region of a front layer portion of each of the plurality of element formation regions;
conductive pads connected to the contact regions of the respective plurality of element formation regions, the conductive pads extending across the element isolation region;
a first insulating layer covering the first semiconductor layer and the conductive pads;
a second semiconductor layer disposed on the first insulating layer and provided with a second active element;
a second insulating layer covering the second semiconductor layer; and
conductive plugs each embedded in a connection hole extending from the second insulating layer to a corresponding conductive pad, wherein each conductive plug includes a material that is identical to a material of the corresponding conductive pad, wherein each conductive plug is formed integrally with the corresponding conductive pad, and
wherein each conductive pad is larger in area in plan view than the corresponding conductive plug.

2. The semiconductor apparatus according to claim 1 , wherein
the conductive pad and the conductive plug each include a metal material with a high melting point.

3. The semiconductor apparatus according to claim 1 , wherein
the first active element includes a photodiode and a transfer transistor including a source region electrically connected to a cathode region of the photodiode and a drain region electrically connected to the conductive plug, and
the second active element includes an amplifying transistor including a gate electrode electrically connected to the conductive plug.

4. A method for manufacturing a semiconductor apparatus, the method comprising:
forming, in a first semiconductor layer, a plurality of element formation regions delimited by element isolation regions;
forming contact regions each on a side of the element isolation region of a front layer portion of each of the plurality of element formation regions adjacent to one another via the element isolation regions;
forming pad cores, via an etching stopper film, on the contact regions of the respective plurality of element formation regions, the pad cores extending across the element isolation regions;
forming a first active element in each of the plurality of element formation regions;
forming a first insulating layer covering the first semiconductor layer and the pad cores;
disposing a second semiconductor layer on the first insulating layer;
executing a step including thermal treatment to form a second active element in the second semiconductor layer;
forming a second insulating layer covering the second semiconductor layer;
forming connection holes each extending from the second insulating layer to the pad cores;
for each of the connection holes, removing the pad core and the etching stopper film through the connection hole to form a space portion communicating with the connection hole; and
embedding a conductive material into the space portions and the connection holes to form a conductive pad connected to the contact regions and a conductive plug integrated with the conductive pad,
wherein the conductive pads are larger in area in plan view than the conductive plugs.

5. The method for manufacturing a semiconductor apparatus, the method according to claim 4 , wherein
the pad core includes a non-doped polycrystal silicon film.

6. The method for manufacturing a semiconductor apparatus, the method according to claim 5 , wherein
the step of forming the second active element includes
a step of executing thermal treatment to form, on a front surface of the second semiconductor layer, a gate insulating film including a thermal oxide film, and
a step of executing thermal treatment to form a source region and a drain region in a front layer portion of the second semiconductor layer.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Fujii Nobutoshi
• Sejima Koichi
• Saga Koichiro
• Miyake Shinichi

Classifications

• H10P14/60

  of insulating materials · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title