Mating backplane for high speed, high density electrical connector

Patent metadata

Field	Value
Publication number	US-12309915-B2
Application number	US-202418583199-A
Country	US
Kind code	B2
Filing date	Feb 21, 2024
Priority date	Nov 21, 2014
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.

First claim

What is claimed is:

1. A printed circuit board comprising:
a plurality of layers including conductive layers separated by dielectric layers; and
an array of via patterns formed in one or more of the plurality of layers, the array of via patterns including a first via pattern and a second via pattern, the first and second via patterns each comprising:
first and second signal vias connected to respective signal traces on one or more of the conductive layers;
ground vias extending through at least some layers of the plurality of layers; and
shadow vias located on opposite sides of each of the first and second signal vias and extending through at least some layers of the plurality of layers, wherein each of the shadow vias comprises a non-plated air hole.

2. The printed circuit board as defined in claim 1 , wherein the shadow vias are located in proximity to the first and second signal vias.

3. The printed circuit board as defined in claim 1 , wherein the shadow vias comprise first and second shadow vias located in proximity to each of the first signal vias and third and fourth shadow vias located in proximity to each of the second signal vias.

4. The printed circuit board as defined in claim 3 , wherein the first and second shadow vias are located on opposite sides of each of the first signal vias and the third and fourth shadow vias are located on opposite sides of each of the second signal vias.

5. The printed circuit board as defined in claim 1 , wherein the shadow vias extend to a predetermined depth in the plurality of layers.

6. The printed circuit board as defined in claim 1 , wherein the shadow vias extend through the plurality of layers.

7. The printed circuit board as defined in claim 1 , wherein each of the shadow vias is in electrical contact with one or more of the conductive layers.

8. The printed circuit board as defined in claim 1 , wherein each of the shadow vias is smaller in diameter than the first and second signal vias.

9. The printed circuit board as defined in claim 1 , wherein each of the shadow vias is smaller in diameter than the ground vias.

10. The printed circuit board as defined in claim 1 , wherein at least one of the conductive layers of the plurality of layers is removed in an area around the first and second signal vias to form an antipad, and wherein each of the shadow vias is located, at least partially, within the antipad.

11. The printed circuit board as defined in claim 1 , wherein the array of via patterns includes columns of via patterns and wherein the first via pattern is located in a first column and the second via pattern is located in a second column.

12. A method for making a printed circuit board, comprising:
forming a plurality of layers including conductive layers separated by dielectric layers;
forming first and second signal vias extending through one or more of the plurality of layers; and
forming shadow vias associated with each of the first and second signal vias, the shadow vias extending through one or more of the plurality of layers, wherein forming shadow vias includes forming the shadow vias on a first line that passes through one of the first and second signal vias, the first line being perpendicular to a second line that passes through the first and second signal vias, wherein forming shadow vias includes forming shadow vias that are free of conductive material.

13. The method as defined in claim 12 , further comprising forming ground vias extending through one or more of the plurality of layers.

14. A method for making a printed circuit board, comprising:
forming a plurality of layers including conductive layers separated by dielectric layers;
forming first and second signal vias extending through one or more of the plurality of layers; and
forming shadow vias associated with each of the first and second signal vias, the shadow vias extending through one or more of the plurality of layers, wherein forming shadow vias includes forming the shadow vias on a first line that passes through one of the first and second signal vias, the first line being perpendicular to a second line that passes through the first and second signal vias, wherein forming shadow vias includes forming additional shadow vias located on the second line that passes through the first and second signal vias.

15. A method for making a printed circuit board, comprising:
forming a plurality of layers including conductive layers separated by dielectric layers;
forming first and second signal vias extending through one or more of the plurality of layers; and
forming shadow vias associated with each of the first and second signal vias, the shadow vias extending through one or more of the plurality of layers, wherein forming shadow vias includes forming the shadow vias on a first line that passes through one of the first and second signal vias, the first line being perpendicular to a second line that passes through the first and second signal vias, wherein the shadow vias are formed with smaller diameters than the first and second signal vias in one or more layers of the plurality of layers.

16. A method for making a printed circuit board, comprising:
forming a plurality of layers including conductive layers separated by dielectric layers;
forming first and second signal vias extending through one or more of the plurality of layers; and
forming shadow vias associated with each of the first and second signal vias, the shadow vias extending through one or more of the plurality of layers, wherein forming the shadow vias includes forming non-plated air holes.

Assignees

• Amphenol Corp

Inventors

• Gailus Mark W
• Cartier Jr Marc B
• Sivarajan Vysakh
• Levine David

Classifications

• H05K2201/09545

  Plated through-holes or blind vias without lands · CPC title

• H05K2201/09318

  Core having one signal plane and one power plane · CPC title

• H05K2201/07

  Electric details · CPC title

• H05K1/0216

  Reduction of cross-talk, noise or electromagnetic interference (grounding H05K1/0215) · CPC title

• H05K2201/10189

  Non-printed connector · CPC title