Module compliance boards for quad small form-factor pluggable (qsfp) devices

Patent metadata

Field	Value
Publication number	US-2016309576-A1
Application number	US-201514690428-A
Country	US
Kind code	A1
Filing date	Apr 19, 2015
Priority date	Apr 19, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

An optimized ground (GND) network connection is provided between a Quad Small Form-factor Pluggable (QSFP) connector and a printed circuit board (PCB). The optimized GND network creates a “GND Island” around the signal pads by adding GND cage around the signal pads (at the empty corridor and in front of QSFP pads) and GND TH (ground through hole) vias from both sides of signal pads (at the empty corridor and in front of QSFP pads).

First claim

1 . A printed circuit board comprising:
a first ground layer and a second ground layer and a signal layer between the first and second ground layers; at least one island surrounding at least two signal pads at the first ground layer, the signal pads in electrical communication with the second layer to define a current pathway; and, a plurality of vias extending from the first ground layer to the second ground layer to define an alternate current pathway.

2 . The printed circuit board of claim 1 , wherein the at least one island includes a plurality of islands oppositely disposed from each other so as to be arranged in rows on the first ground layer to define a corridor intermediate the rows.

3 . The printed circuit board of claim 2 , wherein the first ground layer includes at least one ground pad at the ends of the islands.

4 . The printed circuit board of claim 3 , wherein the at least one ground pad includes a plurality of ground pads extending along the rows.

5 . The printed circuit board of claim 4 , wherein the signal layer comprises:
a conductor extending along the signal layer and aligned with the corridor of the first ground layer, and, a plurality of conductive leads aligned with a corresponding ground pad, and in electrical communication with the conductor and the corresponding ground pad.

6 . The printed circuit board of claim 5 , additionally comprising: ground shielding vias extending between the first ground layer and the second ground layer.

7 . The printed circuit board of claim 1 , wherein the plurality of vias include, a plurality of through holes for sinking current.

8 . The printed circuit board of claim 1 , wherein the first ground layer and the third layer include a copper layer.

9 . The printed circuit board of claim 1 , wherein the third ground layer includes a plurality of voids, each of the voids in electrical communication with the signal pad of the first ground layer.

10 . A method for electric current circulation, comprising:
obtaining a printed circuit board comprising:
a first ground layer and a second ground layer and a signal layer between the first and second ground layers;
at least one island surrounding at least two signal pads at the first ground layer, the signal pads in electrical communication with the second layer to define a current pathway;
at least two ground pads disposed at opposite sides of the at least one island; and,
a plurality of vias in electrical communication with the ground pads and extending from the first ground layer to the second ground layer to define an alternate current pathway;
placing an electrical connector into electrical communication with the signal pads and the surface of the first ground layer; and, passing electrical current through the connector, such that 1) current flow from the electrical pads to the signal layer defines a current pathway, and, 2) current flow through the plurality of vias extending from the first ground layer to the second ground layer defines an alternate current pathway.

11 . The method of claim 10 , additionally comprising: sinking the electrical current by the plurality of vias.

12 . A printed circuit board comprising:
a first ground layer and a second ground layer and a signal layer between the first and second ground layers; a plurality of islands, each of the islands surrounding at least two signal pads at the first ground layer, the signal pads in electrical communication with the second layer to define a current pathway, and the islands of the plurality of islands oppositely disposed from each other so as to be arranged in rows on the first ground layer to define a corridor intermediate the rows; and, a plurality of vias extending from the first ground layer to the second ground layer to define an alternate current pathway.

13 . The printed circuit board of claim 12 , wherein the first ground layer includes at least one ground pad at the ends of the islands.

14 . The printed circuit board of claim 13 , wherein the at least one ground pad includes a plurality of ground pads extending along the rows.

15 . The printed circuit board of claim 14 , wherein the signal layer comprises ground cages, the ground cages comprising:
a conductor extending along the signal layer and aligned with the corridor of the first ground layer; and, a plurality of conductive leads aligned with a corresponding ground pad, and in electrical communication with the conductor and the corresponding ground pad.

16 . The printed circuit board of claim 15 , additionally comprising: ground shielding vias extending between the first ground layer and the second ground layer.

17 . The printed circuit board of claim 12 , wherein the plurality of vias include, a plurality of through holes for sinking current.

18 . The printed circuit board of claim 12 , wherein the first ground layer and the third layer include a copper layer.

19 . The printed circuit board of claim 12 , wherein the third ground layer includes a plurality of voids, each of the voids in electrical communication with the signal pad of the first ground layer.

Assignees

• Mellanox Technologies Ltd

Inventors

• SHARAV Boris
• Malkiman Yonatan

Classifications

• H05K1/0298

  Multilayer circuits · CPC title

• H05K1/111 Primary

  Pads for surface mounting, e.g. lay-out · CPC title

• H05K1/0213 Primary

  Electrical arrangements not otherwise provided for · CPC title

• H05K1/115

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K1/09

  Use of materials for the {conductive, e.g. } metallic pattern · CPC title