Three-dimensional memory device with backside interconnect structures

Patent metadata

Field	Value
Publication number	US-12302573-B2
Application number	US-202418746944-A
Country	US
Kind code	B2
Filing date	Jun 18, 2024
Priority date	Apr 14, 2020
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

A three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers over a first side of a second semiconductor layer, channel structures extending vertically through the memory stack and into the second semiconductor layer, source contacts in contact with a second side of the second semiconductor layer opposite to the first side; and a backside interconnect layer over the second side of the second semiconductor layer and including interlayer dielectric (ILD) layers and a source line mesh on the ILD layers. The source contacts are distributed on a side of the source line mesh. The source contacts extend through the ILD layers and into the second semiconductor layer.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers over a first side of a second semiconductor layer;
channel structures extending vertically through the memory stack and into the second semiconductor layer;
source contacts in contact with a second side of the second semiconductor layer opposite to the first side; and
a backside interconnect layer over the second side of the second semiconductor layer and comprising interlayer dielectric (ILD) layers and a source line mesh on the ILD layers, wherein the source contacts are distributed on a side of the source line mesh, and the source contacts extend through the ILD layers and into the second semiconductor layer.

2. The 3D memory device of claim 1 , wherein the memory stack comprises a core array region, and at least a part of the source contacts are in the core array region.

3. The 3D memory device of claim 1 , further comprising a first semiconductor layer between the memory stack and the second semiconductor layer, wherein the channel structures each comprises a semiconductor channel and a memory film surrounding a portion of the semiconductor channel, and the first semiconductor layer surrounds a part of the channel structures and is in contact with the semiconductor channel.

4. The 3D memory device of claim 3 , wherein the memory film comprises a first portion and a second portion distributed on opposite sides of the first semiconductor layer, the first portion of the memory film is in the second semiconductor layer, and the second portion of the memory film is in the memory stack.

5. The 3D memory device of claim 1 , wherein the source contacts comprise a via contact.

6. The 3D memory device of claim 1 , wherein the source contacts comprise a metal layer and an adhesive layer surrounding the metal layer.

7. The 3D memory device of claim 1 , further comprising a gate line slit extending vertically through the memory stack, wherein a part of the source contacts is over the gate line slit, and a portion of one of the source contacts and the gate line slit overlap along a first lateral direction.

8. The 3D memory device of claim 1 , further comprising contacts through the second semiconductor layer, wherein a first set of the contacts are in contact with the source line mesh.

9. The 3D memory device of claim 8 , wherein the memory stack comprises two core array regions having the channel structures and a staircase region between the two core array regions in a first lateral direction in a plan view.

10. The 3D memory device of claim 9 , wherein the backside interconnect layer further comprises source select gate (SSG) lines in the plan view, and a second set of contacts are distributed below and in contact with the SSG lines.

11. The 3D memory device of claim 9 , wherein the backside interconnect layer further comprises a power line mesh in the plan view, and a third set of contacts are distributed below and in contact with the power line mesh.

12. The 3D memory device of claim 11 , wherein each of the power line mesh and the source line mesh has a comb-like shape.

13. A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers over a first side of a second semiconductor layer;
channel structures extending vertically through the memory stack and into the second semiconductor layer;
source contacts in contact with a second side of the second semiconductor layer opposite to the first side, wherein the source contacts comprise a metal layer and an adhesive layer surrounding the metal layer;
a backside interconnect layer over the second side of the second semiconductor layer and comprising interlayer dielectric (ILD) layers and a source line mesh on the ILD layers, wherein the source contacts are distributed on a side of the source line mesh and extend through the ILD layers and into the second semiconductor layer; and
a first semiconductor layer between the memory stack and the second semiconductor layer, wherein the channel structures each comprises a semiconductor channel and a memory film surrounding a portion of the semiconductor channel, and the first semiconductor layer surrounds a part of the channel structures and is in contact with the semiconductor channel.

14. The 3D memory device of claim 13 , wherein the memory stack comprises a core array region, and at least a part of the source contacts are in the core array region.

15. The 3D memory device of claim 13 , wherein the memory film comprises a first portion and a second portion distributed on opposite sides of the first semiconductor layer, the first portion of the memory film is in the second semiconductor layer, and the second portion of the memory film is in the memory stack.

16. The 3D memory device of claim 13 , further comprising a gate line slit extending vertically through the memory stack, wherein a part of the source contacts is over the gate line slit, and a portion of one of the source contacts and the gate line slit overlap along a first lateral direction.

17. The 3D memory device of claim 13 , further comprising contacts through the second semiconductor layer, wherein a first set of the contacts are in contact with the source line mesh.

18. The 3D memory device of claim 17 , wherein the backside interconnect layer further comprises source select gate (SSG) lines in a plan view, and a second set of the contacts are distributed below and in contact with the SSG lines.

19. A method for forming a three-dimensional (3D) memory device, comprising:
forming a memory stack comprising interleaved conductive layers and dielectric layers over a first side of a second semiconductor layer;
forming channel structures extending vertically through the memory stack and into the second semiconductor layer;
forming source contacts in contact with a second side of the second the semiconductor layer opposite to the first side; and
forming a backside interconnect layer over the second side of the second semiconductor layer and comprising interlayer dielectric (ILD) layers and a source line mesh on the ILD layers, wherein the source contacts are distributed on a side of the source line mesh and extend through the ILD layers and into the second semiconductor layer.

20. The method of claim 19 , further comprising:
forming a peripheral circuit on a first substrate;
forming the memory stack and the channel structures on a second substrate;
bonding the first substrate and the second substrate in a face-to-face manner, wherein the channel structures and the peripheral circuit are between the first substrate and the second substrate;
thinning the second substrate to form a semiconductor layer;
forming the ILD layers over the semiconductor layer; and
forming the source contacts and the source line mesh on the ILD layers.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Kun
• Zhang Zhong
• Liu Lei
• Zhou Wenxi
• Xia Zhiliang

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/301

  Bonding techniques, e.g. hybrid bonding · CPC title

• H10W72/963

  Providing mechanical bonding or support, e.g. dummy bond pads · CPC title