Semiconductor device including hard macro

Patent metadata

Field	Value
Publication number	US-12293958-B2
Application number	US-202117236018-A
Country	US
Kind code	B2
Filing date	Apr 21, 2021
Priority date	Oct 26, 2020
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate which comprises a first surface and a second surface opposing each other, and a hard macro which is disposed on the first surface of the substrate. The hard macro comprises a cell area and a halo area formed along the periphery of the cell area. In addition, the hard macro comprises a first connection wiring disposed at a first metal level and having at least a part extending from the cell area to the halo area, a first power rail which is disposed on the second surface of the substrate and receives a first voltage, and a first through via which penetrates the halo area and the substrate to connect the first power rail and the first connection wiring and is a single structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate which comprises a first surface and a second surface opposing each other;
a hard macro which is disposed on the first surface of the substrate and comprises a cell area and a halo area formed along a periphery of the cell area, and a first connection wiring disposed at a first metal level, the first connection wiring including a first wire, the first wire comprising a single linear segment that extends continuously from the cell area to the halo area at the first metal level;
a first power rail which is disposed on the second surface of the substrate and receives a first voltage; and
a first through via which penetrates the halo area and the substrate to connect the first power rail and the first connection wiring,
wherein the first through via is a single structure, and
wherein a portion of a bottom surface of the first wire directly contacts an upper surface of the first through via.

2. The semiconductor device of claim 1 ,
wherein the hard macro further comprises a second connection wiring disposed on the first connection wiring, and
wherein the second connection wiring does not overlap the halo area in a direction from the first surface of the substrate toward the second surface.

3. The semiconductor device of claim 1 , wherein a width of the first through via is reduced in a direction from the second surface of the substrate toward the first surface.

4. The semiconductor device of claim 1 , further comprising:
a power wiring which is disposed on the first power rail; and
a power via which connects the power wiring and the first power rail,
wherein a voltage provided to the first power rail is distributed by the power wiring and the power via.

5. The semiconductor device of claim 4 , wherein a width of the power via is reduced in a direction from the first surface of the substrate toward the second surface.

6. The semiconductor device of claim 1 , further comprising:
a second power rail which receives a second voltage different from the first voltage;
a second connection wiring which is disposed at the first metal level and has at least a part extending from the cell area to the halo area; and
a second through via which connects the second power rail and the second connection wiring.

7. The semiconductor device of claim 6 , wherein the first voltage is a power supply voltage, and the second voltage is a ground voltage.

8. The semiconductor device of claim 1 ,
wherein the cell area comprises a first side and a second side which oppose each other in a length direction of the substrate and a third side and a fourth side which connect the first side and the second side and oppose each other in a width direction of the substrate,
wherein the first through via is one of a plurality of first through vias, and
wherein the plurality of first through vias are disposed in the halo area on at least one of the first through fourth sides.

9. The semiconductor device of claim 1 , further comprising:
a logic area which is disposed on the first surface of the substrate and spaced apart from the hard macro and comprises a second connection wiring disposed at the first metal level;
a signal line which is disposed on the second surface of the substrate and spaced apart from the first power rail; and
a second through via which penetrates the substrate to connect the signal line and the second connection wiring.

10. The semiconductor device of claim 9 , further comprising a third connection wiring which is disposed on the first connection wiring and the second connection wiring to connect the first connection wiring and the second connection wiring.

11. The semiconductor device of claim 1 , wherein at least a part of the first power rail is buried in the substrate, and the first through via is directly connected to the first power rail.

12. A semiconductor device comprising:
a first substrate which comprises a power rail for providing a voltage and a signal line for transmitting a signal;
a second substrate which is disposed on the first substrate;
a logic area which is disposed on an upper surface of the second substrate;
a hard macro which is disposed on the upper surface of the second substrate and comprises a cell area and a halo area formed along a periphery of the cell area;
a first through via which is disposed in the halo area, penetrates the second substrate, and is connected to the power rail to provide the voltage to the hard macro; and
a second through via which is disposed in the logic area, penetrates the second substrate, and is connected to the signal line to provide the signal to the hard macro,
wherein the hard macro comprises a first connection wiring including a first wire, the first wire comprising a single linear segment that extends continuously from the cell area to the halo area at a same vertical level, and
wherein a portion of the bottom surface of the first wire directly contact an upper surface of the first through via.

13. The semiconductor device of claim 12 ,
wherein the logic area comprises a second connection wiring disposed at the first metal level,
wherein the first through via is directly connected to the first connection wiring, and
wherein the second through via is directly connected to the second connection wiring.

14. A semiconductor device comprising:
a substrate which comprises a first surface and a second surface opposing each other;
a hard macro which is disposed on the first surface of the substrate and comprises a cell area and a halo area formed along a periphery of the cell area, and a first connection wiring disposed at a first metal level, the first connection wiring including a first wire, the first wire comprising a single linear segment that extends continuously from the cell area to the halo area at the first metal level;
a logic area which is disposed on the first surface of the substrate, is spaced apart from the hard macro, and comprises a second connection wiring disposed at the first metal level;
first and second power rails which are disposed on the second surface of the substrate and spaced apart from each other;
a first through via which is disposed in the halo area of the hard macro and penetrates the halo area and the substrate to connect the first power rail and the first connection wiring; and
a second through via which is disposed in the halo area of the hard macro and penetrates the substrate to connect the second power rail and the second connection wiring,
wherein a portion of a bottom surface of the first wire directly contacts an upper surface of the first through via.

15. The semiconductor device of claim 14 , wherein a width of the first through via and a width of the second through via are reduced in a direction from the second surface of the substrate toward the first surface.

16. The semiconductor device of claim 14 , wherein the logic area further comprises a third connection wiring disposed at the first metal level, the semiconductor device further comprising:
a signal line which is disposed on the second surface of the substrate; and
a third through via which penetrates the substrate to connect the signal line and the third connection wiring.

17. The semiconductor device of claim 16 , wherein the third connection wiring is connected to the first connection wiring.

18. The semiconductor device of claim 16 ,
wherein the logic area further comprises a third-fourth connection wiring disposed on the first connection wiring and the third connection wiring, and
wherein th

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jong Doo
• Park Sang Do

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/212

  Top-view shapes or dispositions, e.g. top-view layouts of the vias · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/427 Primary

  Power or ground buses · CPC title