Post-grind die backside power delivery

Patent metadata

Field	Value
Publication number	US-10032707-B2
Application number	US-201615391587-A
Country	US
Kind code	B2
Filing date	Dec 27, 2016
Priority date	Dec 27, 2016
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a backside. The top side may include a plurality of pad connections. The plurality of vias may extend through the material layer from the top side to the backside. The plurality of metal channels may be in contact with the backside. Each of the plurality of metal channels may be in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias.

First claim

The invention claimed is:

1. A die comprising:
a material layer having a top side and a backside, the top side including a plurality of pad connections, the backside including a power connection;
a plurality of vias extending through the material layer from the top side to the backside; and
a plurality of metal channels in contact with the backside, each of the plurality of metal channels in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias, at least one of the plurality of metal channels in electrical communication with the power connection, wherein a first metal channel of the plurality of metal channels is located adjacent a reference channel within the material layer.

2. The die of claim 1 , wherein the material layer is comprised of a semiconductor material.

3. The die of claim 1 , wherein the die is one of a plurality of dies located on a semiconductor wafer.

4. The die of claim 1 , wherein the top side comprises integrated circuitry in electrical communication with the plurality of pad connections.

5. The die of claim 1 , wherein each of the plurality of metal channels are substantially wider than a width of each of a plurality of signal traces located on the top side of the material layer.

6. The die of claim 1 , wherein each of the plurality of metal channels has a width at least one order of magnitude greater than a width of each of a plurality of signal traces located on the top side of the material layer.

7. The die of claim 1 , wherein the die is a component of a memory board, a motherboard, a sound card, or a video card.

8. The die of claim 1 , wherein the plurality of metal channels are manufactured from a metal selected from the group consisting of copper, gold, platinum, or aluminum.

9. A die comprising:
a material layer having a top side and a backside, the top side including a plurality of pad connections, the backside including a power connection;
a plurality of vias extending through the material layer from the top side to the backside;
a first metal layer in contact with the backside, the first metal layer in electrical communication with at least one of the plurality of pad connections and a first subset of the plurality of vias; and
a second metal layer located adjacent to the first metal layer and separated by a dielectric, the second metal layer in electrical communication with a second subset of the plurality of vias, the second metal layer being a reference plane,
wherein the first metal layer is in electrical communication with the power connection.

10. The die of claim 9 , wherein the top side comprises integrated circuitry in electrical communication with the plurality of pad connections.

11. The die of claim 9 , wherein the die is a component of a memory board, a motherboard, a sound card, or a video card.

12. The die of claim 9 , wherein the first metal layer and the second metal layer are manufactured from a metal selected from the group consisting of copper, gold, platinum, or aluminum.

13. The die of claim 9 , further comprising:
a second material layer having a second top side and a second backside, the second top side including a second plurality of pad connections connected to the plurality of pad connections;
a second plurality of vias extending through the second material layer from the second top side to the second backside;
a third metal layer in contact with the second backside, the third metal layer in electrical communication with at least one of the second plurality of pad connections and a first subset of the second plurality of vias; and
a fourth metal layer located adjacent to the third metal layer and separated by a second dielectric, the fourth metal layer in electrical communication with a second subset of the second plurality of vias.

14. A microelectronics package comprising:
a substrate;
a first die at least partially embedded within the substrate, the first die comprising:
a first material layer having a first top side and a first backside, the first top side including a first plurality of pad connections,
a first plurality of vias extending through the first material layer from the first top side to the first backside, and
a first plurality of metal channels in contact with the first backside, each of the first plurality of metal channels in electrical communication with at least one of the first plurality of pad connections and at least one of the first plurality of vias, wherein the first plurality of metal channels form a reference plane; and

a second die comprising:
a second material layer having a second top side and a second backside, the second top side including a second plurality of pad connections in electrical communication with the first plurality of pad connections,
a second plurality of vias extending through the second material layer from the second top side to the second backside, and
a second plurality of metal channels in contact with the second backside, each of the second plurality of metal channels in electrical communication with at least one of the second plurality of pad connections and at least one of the second plurality of vias.

15. The microelectronics package of claim 14 , further comprising:
a third die; and
a bridge electrically connecting third die to at least one of the first die and the second die.

16. The microelectronics package of claim 14 , wherein the first material layer and the second material layer are comprised of a semiconductor based material.

17. The microelectronics package of claim 14 , wherein each of the first plurality of metal channels are substantially wider than a width of each of a first plurality of signal traces located on the first top side of the first material layer.

18. The microelectronics package of claim 14 , wherein each of the second plurality of metal channels has a width at least one order of magnitude greater than a width of each of a second plurality of signal traces located on the second top side of the second material layer.

19. A microelectronics package comprising:
a substrate;
a first die at least partially embedded within the substrate, the first die comprising:
a first material layer having a first top side and a second backside, the first top side including a first plurality of pad connections,
a first plurality of vias extending through the first material layer from the first top side to the first backside,
a first metal layer in contact with the first backside, the first metal layer in electrical communication with at least one of the first plurality of pad connections and a first subset of the first plurality of vias, and
a second metal layer located adjacent to the first metal layer and separated by a first dielectric, the second metal layer in electrical communication with a second subset of the first plurality of vias, the second metal layer being reference plane;

a second die comprising:
a second material layer having a second top side and a second backside, the second top side including a second plurality of pad connections in electrical communication with the first plurality of pad connections,
a second plurality of vias extending through the second material layer from the second top side to the second backside, and
a third metal layer in contact with the second backside, the third metal layer in electrical communication with at least one of the second plurality of pad connections and a first subset of the second plurality of vias, and
a fourth metal layer located adjacent to the th

Assignees

• Intel Corp

Inventors

• Lai Min-Tih Ted
• Leuten Tyler
• Pon Florence R

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title