Semiconductor devices having power rails and signal tracks arranged in different layer

Patent metadata

Field	Value
Publication number	US-11756876-B2
Application number	US-202016837918-A
Country	US
Kind code	B2
Filing date	Apr 1, 2020
Priority date	Apr 1, 2020
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

A semiconductor device includes a base, source, drain and gate electrodes, signal tracks and a power mesh. The source, drain and gate electrodes are arranged on a surface of the base, wherein the gate electrodes are extended along a first direction. The signal tracks arranged above the first surface of the base and above the source and drain electrodes and the gate electrodes, wherein the signal tracks are extended along the first directions. A power mesh is arranged below the first surface of the base, the power mesh comprising first power rails extended in the second direction and second power rails extended in a first direction, wherein the second direction is substantially perpendicular to the first direction.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a base having a first surface;
source and drain electrodes and gate electrodes arranged on the first surface of the base, wherein the gate electrodes are extended along a first direction;
signal tracks arranged above the first surface of the base and above the source and drain electrodes and the gate electrodes, wherein the signal tracks are extended along the first direction;
a power mesh arranged below the first surface of the base, the power mesh comprising first power rails extended in a second direction and second power rails extended in the first direction, wherein the second direction is substantially perpendicular to the first direction; and
first vias through the base for coupling the first power rails to the second power rails in a third direction substantially perpendicular to the first surface of the base,
wherein the first vias are aligned with crossings of the first power rails and the second power rails in the third direction.

2. The semiconductor device of claim 1 , further comprising second vias through the base for coupling the source and drain electrodes to the power mesh in the third direction.

3. The semiconductor device of claim 1 , further comprising second vias for coupling the source and drain electrodes to the signal tracks in the third direction.

4. The semiconductor device of claim 3 , wherein at least two of the second vias are arranged in rows along the second direction.

5. The semiconductor device of claim 1 ,
wherein the source and drain electrodes are arranged in an array, and
wherein each of the source and drain electrodes in a row in the second direction has a first edge and a second edge opposite the second edge, wherein each first edge of the source and drain electrodes are aligned with each other, and wherein each second edge of the source and drain electrodes are aligned with each other.

6. The semiconductor device of claim 1 , further comprising second vias for coupling the gate electrodes to the signal tracks.

7. The semiconductor device of claim 6 , wherein the second vias are arranged on gate electrodes in row along the second direction.

8. The semiconductor device of claim 1 , wherein the first power rails are arranged closer to the first surface of the base than the second power rails.

9. The semiconductor device of claim 1 , wherein the power mesh further comprising third power rails further away from the first surface of the base than the second power rails, and wherein the third power rails are extended in the second direction.

10. The semiconductor device of claim 1 , wherein each of the signal tracks couples two gate electrodes adjacent and aligned in the first direction with two second vias aligned in the first direction.

11. The semiconductor device of claim 10 , wherein the second vias corresponding to adjacent signal tracks are arranged in rows along the second direction.

12. The semiconductor device of claim 1 , wherein the base comprises more than one substrate, and wherein source and drain electrodes and gate electrodes arranged on a first surface of a first substrate, and wherein the first power rails are arranged on a second surface of the first substrate opposite the first surface of the first substrate.

13. The semiconductor device of claim 1 , wherein the base is a single substrate, wherein the second power rails are arranged on the second surface of the base.

14. The semiconductor device of claim 1 , wherein the power mesh is embedded in the base.

15. The semiconductor device of claim 1 , wherein the power mesh comprises more than three layers power rails, and the power rails electrically connect to the signal tracks with second vias through the base.

16. The semiconductor device of claim 1 , wherein the first power rails and the second power rails are substantially perpendicular to each other.

17. A semiconductor device, comprising:
a base having a first surface;
source and drain electrodes and gate electrodes arranged on the first surface of the base, wherein each of the source and drain electrodes has a first edge and a second edge opposite the second edge, wherein each first edge of the source and drain electrodes are aligned with each other, and wherein each second edge of the source and drain electrodes are aligned with each other;
signal tracks arranged above the first surface of the base and above the source and drain electrodes and the gate electrodes;
a power mesh comprising first power rails extended in a second direction and second power rails extended in a first direction, wherein the second direction is perpendicular to the first direction, wherein the power mesh is arranged below base having a first surface; and
first vias through the base for coupling the first power rails to the second power rails in a third direction substantially perpendicular to the first surface of the base,
wherein the first vias are aligned with crossings of the first power rails and the second power rails in the third direction.

18. The semiconductor device of claim 17 , further comprising second vias for coupling the source and drain electrodes to the signal tracks, wherein at least two of the vias are arranged in row along the second direction.

19. The semiconductor device of claim 17 , further comprising second vias for coupling the gate electrodes to the signal tracks, wherein the vias are arranged on gate electrodes in row in the second direction.

20. A semiconductor device, comprising:
a base,
source and drain electrodes and gate electrodes on the base, wherein the gate electrodes are extended along a first direction;
signal tracks extended along the first direction;
a power mesh comprising first power rails extended in the second direction and second power rails extended in the first direction, wherein the second direction is substantially perpendicular to the first direction; and
first vias through the base for coupling the first power rails to the second power rails in a third direction substantially perpendicular to a first surface of the base,
wherein the first vias are aligned with crossings of the first power rails and the second power rails in the third direction, and
wherein the signal tracks and the power mesh are arranged at different height levels.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lai Wei-An
• Lin Wei-Cheng
• Tzeng Jiann-Tyng

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/427 Primary

  Power or ground buses · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title