Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Patent metadata

Field	Value
Publication number	US-9870962-B1
Application number	US-201715719615-A
Country	US
Kind code	B1
Filing date	Sep 29, 2017
Priority date	Apr 4, 2016
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such fill cells further include geometry to enable non-contact evaluation of interlayer overlap shorts and/or leakages.

First claim

The invention claimed is:

1. An integrated circuit (IC) that includes a multiplicity of standard cell library compatible, non-contact electrical measurement (NCEM)-enabled fill cells, each of said NCEM-enabled fills cells including:
at least first and second power rails, each formed in a conductive layer, and each extending longitudinally in a first direction, the power rails configured for abutted instantiation with logic cells in the standard cell library;
a plurality of gate (GATE) stripes, each extending longitudinally, in a second direction perpendicular to the first direction, from at least the first power rail to at least the second power rail, each of the GATE stripes having a uniform transverse thickness and a uniform center-to-center spacing (CPP) between adjacent GATE stripes;
an NCEM pad, comprised of:
at least three first-direction stripes, each formed in a conductive layer, each extending longitudinally in the first direction, and each positioned in the transverse direction between the first and second power rails;
at least three second-direction stripes, each formed in a conductive layer, each extending longitudinally in the second direction, each positioned longitudinally between the first and second power rails, and each positioned transversely between adjacent GATE stripes, such that the center-to-center spacing between adjacent second-direction stripes is CPP;
wherein each of the first-direction stripes overlaps, and is connected to, each of the second-direction stripes;

at least one interlayer overlap test area, defined by a first patterned feature and a second patterned feature, not electrically connected to, the first patterned feature, the first and second patterned features partially overlapping to define a rectangular test area characterized by a major dimension and a minor dimension; and,
pad/ground wiring that (i) connects one of the first or second patterned features to the NCEM pad and (ii) connects the other of the first or second patterned features to at least one of the power rails.

2. An IC, as defined in claim 1 , wherein the NCEM-enabled fill cells are configured as interlayer-overlap-short-configured fill cells.

3. An IC, as defined in claim 1 , wherein the NCEM-enabled fill cells are configured as interlayer-overlap-leakage-configured fill cells.

4. An IC, as defined in claim 1 , wherein the NCEM pads include four first-direction stripes, each formed in a conductive layer, each extending longitudinally in the first direction, and each positioned in the transverse direction between the first and second power rails.

5. An IC, as defined in claim 1 , wherein the first-direction stripes are single patterned.

6. An IC, as defined in claim 1 , wherein the first-direction stripes are double patterned.

7. An IC, as defined in claim 1 , wherein the first-direction stripes are triple patterned.

8. An IC, as defined in claim 1 , wherein the second-direction stripes are single patterned.

9. An IC, as defined in claim 1 , wherein the second-direction stripes are double patterned.

10. An IC, as defined in claim 1 , wherein the second-direction stripes are triple patterned.

11. An IC, as defined in claim 1 , wherein the NCEM-enabled fill cells include at least two interlayer overlap test areas, wired in parallel.

12. An IC, as defined in claim 11 , wherein each of the parallel-wired test areas is identically configured.

13. An IC, as defined in claim 1 , in the form of a semiconductor wafer.

14. An IC, as defined in claim 1 , in the form of a semiconductor die.

15. An IC, as defined in claim 1 , in the form of a semiconductor chip.

16. An IC, as defined in claim 1 , wherein the NCEM-enabled fill cells form a design of experiments (DOE) in which some of the NCEM-enabled fill cells differ in terms of the major dimension of their interlayer overlap test area(s).

17. An IC, as defined in claim 1 , wherein the NCEM-enabled fill cells form a DOE in which some of the NCEM-enabled fill cells differ in terms of the minor dimension of their interlayer overlap test area(s).

18. An IC, as defined in claim 1 , wherein the NCEM-enabled fill cells form a DOE in which some of the NCEM-enabled fill cells differ in terms of other patterning within expanded test area(s) that surround the interlayer overlap test area(s).

19. An IC, as defined in claim 1 , further comprising additional, differently configured, NCEM-enabled fill cells, said differently configured fill cells selected from a list that consists of:
tip-to-tip-short-configured, NCEM-enabled fill cells;
tip-to-tip-leakage-configured, NCEM-enabled fill cells;
tip-to-side-short-configured, NCEM-enabled fill cells;
tip-to-side-leakage-configured, NCEM-enabled fill cells;
side-to-side-short-configured, NCEM-enabled fill cells;
side-to-side-leakage-configured, NCEM-enabled fill cells;
L-shape-interlayer-short-configured, NCEM-enabled fill cells;
L-shape-interlayer-leakage-configured, NCEM-enabled fill cells;
diagonal-short-configured, NCEM-enabled fill cells;
diagonal-leakage-configured, NCEM-enabled fill cells;
corner-short-configured, NCEM-enabled fill cells;
corner-leakage-configured, NCEM-enabled fill cells;
interlayer-overlap-short-configured, NCEM-enabled fill cells;
interlayer-overlap-leakage-configured, NCEM-enabled fill cells;
via-chamfer-short-configured, NCEM-enabled fill cells;
via-chamfer-leakage-configured, NCEM-enabled fill cells;
merged-via-short-configured, NCEM-enabled fill cells;
merged-via-leakage-configured, NCEM-enabled fill cells;
snake-open-configured, NCEM-enabled fill cells;
snake-resistance-configured, NCEM-enabled fill cells;
stitch-open-configured, NCEM-enabled fill cells;
stitch-resistance-configured, NCEM-enabled fill cells;
via-open-configured, NCEM-enabled fill cells;
via-resistance-configured, NCEM-enabled fill cells;
metal-island-open-configured, NCEM-enabled fill cells;
metal-island-resistance-configured, NCEM-enabled fill cells;
merged-via-open-configured, NCEM-enabled fill cells; and,
merged-via-resistance-configured, NCEM-enabled fill cells.

Assignees

• Pdf Solutions Inc

Inventors

• Lam Stephen
• Ciplickas Dennis
• Brozek Tomasz
• Cheng Jeremy
• Comensoli Simone
• De Indranil
• Doong Kelvin
• Eisenmann Hans
• Fiscus Timothy
• Haigh Jonathan
• Hess Christopher
• Kibarian John
• Lee Sherry
• Liao Marci
• Lin Sheng-Che
• Matsuhashi Hideki
• Michaels Kimon
• O'Sullivan Conor
• Rauscher Markus
• Rovner Vyacheslav
• Strojwas Andrzej
• Strojwas Marcin
• Taylor Carl
• Vallishayee Rakesh
• Weiland Larg
• Yokoyama Nobuharu

Classifications

• G06F30/30

  Circuit design · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title