Semiconductor device

Patent metadata

Field	Value
Publication number	US-12277983-B2
Application number	US-202118250486-A
Country	US
Kind code	B2
Filing date	Oct 27, 2021
Priority date	Nov 10, 2020
Publication date	Apr 15, 2025
Grant date	Apr 15, 2025

Abstract

The present disclosure relates to a semiconductor device enabling to suppress waste of energy consumption. There is provided a semiconductor device including: an input unit configured to input a charge; a memory unit configured to collect and accumulate a charge from the input unit; and an output unit configured to detect and output a charge accumulated in the memory unit. The memory unit includes a transfer unit to which a plurality of pairs of a gate unit and an accumulation unit is connected, the gate unit selects the accumulation unit that accumulates a charge, the transfer unit transfers a charge from the input unit to the accumulation unit selected by the gate unit, the accumulation unit accumulates a charge transferred from the transfer unit, and the transfer unit transfers a charge accumulated in the accumulation unit selected by the gate unit, to the output unit. The present disclosure can be applied to, for example, an analog memory device.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
an input unit configured to input a charge;
a memory unit configured to collect and accumulate a charge from the input unit; and
an output unit configured to detect and output a charge accumulated in the memory unit, wherein
the memory unit includes a transfer unit to which a plurality of pairs of a gate unit and an accumulation unit is connected,
the gate unit is configured to select the accumulation unit that accumulates a charge,
the transfer unit is configured to transfer a charge from the input unit to the accumulation unit selected by the gate unit,
the accumulation unit is configured to accumulate a charge transferred from the transfer unit, and
the transfer unit is further configured to transfers a charge accumulated in the accumulation unit selected by the gate unit, to the output unit.

2. The semiconductor device according to claim 1 , wherein
the transfer unit and the accumulation unit include a floating region that is not in electrical contact from outside.

3. The semiconductor device according to claim 1 , wherein
the transfer unit and the accumulation unit include a charge accumulation region formation part where a region capable of accumulating a charge is formed by an electric field from outside.

4. The semiconductor device according to claim 1 , wherein
a transfer electrode unit, a gate electrode unit, and an accumulation electrode unit are respectively paired with the transfer unit, the gate unit, and the accumulation unit in an electrically non-contact state,
the transfer electrode unit, the gate electrode unit, and the accumulation electrode unit are electrically separated from each other,
by applying a voltage individually to the transfer electrode unit, the gate electrode unit, and the accumulation electrode unit, an influence of an electric field is applied to the transfer unit, the gate unit, and the accumulation unit, and
the transfer unit, the gate unit, and the accumulation unit are respectively paired with the transfer electrode unit, the gate electrode unit, and the accumulation electrode unit.

5. The semiconductor device according to claim 4 , wherein
a charge inputted from the input unit to the transfer unit is transferred to the accumulation unit via the gate unit and accumulated, based on an operation to individually apply a voltage to the transfer electrode unit, the gate electrode unit, and the accumulation electrode unit and an operation to interrupt the voltage, to generate an electric field or extinguish an electric field in each of the transfer unit, the gate unit, and the accumulation unit, and
the transfer unit, the gate unit, and the accumulation unit are respectively paired with the transfer electrode unit, the gate electrode unit, and the accumulation electrode unit.

6. The semiconductor device according to claim 4 , wherein
a charge accumulated in the accumulation unit is transferred from the transfer unit to the output unit via the gate unit and detected, based on an operation to individually apply a voltage to the transfer electrode unit, the gate electrode unit, and the accumulation electrode unit and an operation to interrupt the voltage, to generate an electric field or extinguish an electric field in each of the transfer unit, the gate unit, and the accumulation unit, and
the transfer unit, the gate unit, and the accumulation unit are respectively paired with the transfer electrode unit, the gate electrode unit, and the accumulation electrode unit.

7. The semiconductor device according to claim 4 , wherein
a charge inputted from the input unit is transported in order of the transfer unit, the gate unit, and the accumulation unit, based on an application of a voltage to the transfer electrode unit, the gate electrode unit, and the accumulation electrode unit to apply an electric field to the transfer unit, the gate unit, and the accumulation unit,
the transfer unit, the gate unit, and the accumulation unit are respectively paired with the transfer electrode unit, the gate electrode unit, and the accumulation electrode unit, and
a charge transferred to the accumulation unit is accumulated, based on an interruption of a voltage of the transfer electrode unit and the gate electrode unit to extinguish an electric field to the transfer unit and the gate unit that are respectively paired with the transfer electrode unit and the gate electrode unit.

8. The semiconductor device according to claim 4 , wherein
a charge accumulated in the accumulation unit is transported in order of the gate unit and the transfer unit, based on an application of a voltage to the accumulation electrode unit paired with the accumulation unit that has accumulated a charge and an application of a voltage to the gate electrode unit and the transfer electrode unit to apply an electric field to the gate unit and the transfer unit that are respectively paired with the gate electrode unit and the transfer electrode unit, and
a charge accumulated in the accumulation unit is transferred to the output unit, based on a transportation of a charge from the transfer unit to the output unit, and an interruption of a voltage of the accumulation electrode unit, the gate electrode unit, and the transfer electrode unit to extinguish an electric field to the accumulation unit, the gate unit, and the transfer unit that are respectively paired with the accumulation electrode unit, the gate electrode unit, and the transfer electrode unit.

9. The semiconductor device according to claim 1 , wherein
the gate unit includes a floating region that is not in electrical contact from outside, or a charge accumulation region formation part where a region accumulates a charge is formed by an electric field from outside.

10. The semiconductor device according to claim 9 , wherein
the floating region or the charge accumulation region formation part is connected to a floating region included in the transfer unit and the accumulation unit.

11. The semiconductor device according to claim 4 , wherein
the transfer unit, the gate unit, and the accumulation unit include a semiconductor layer, and
a floating region in the transfer unit and the accumulation unit is formed by an electric field generated in the transfer unit or the accumulation unit respectively paired with the transfer electrode unit or the accumulation electrode unit based on an application of a voltage to the transfer electrode unit or the accumulation electrode unit.

12. The semiconductor device according to claim 1 , further comprising:
a switch unit configured to switch between connection and interruption between the input unit and the transfer unit of the memory unit.

13. The semiconductor device according to claim 12 , wherein
the input unit includes a semiconductor layer, and
the switch unit is in the semiconductor layer.

14. The semiconductor device according to claim 1 , further comprising:
a switch unit configured to switch between connection and interruption between the output unit and the transfer unit of the memory unit.

15. The semiconductor device according to claim 14 , wherein
the output unit includes a semiconductor layer, and
the switch unit is in the semiconductor layer.

16. The semiconductor device according to claim 1 , wherein
the semiconductor device is configured as an analog memory device.

17. The semiconductor device according to claim 16 , wherein
the semiconductor device is configured as an analog memory array system having an array-shape and including a plurality of the analog memory de

Assignees

• Sony Group Corp

Inventors

• Yoshida Hiroshi
• Okuno Jun
• Koga Hiroki
• SHUTO Yusuke
• Tsukamoto Takeo

Classifications

• H10B43/30

  characterised by the memory core region · CPC title

• H10B41/30

  characterised by the memory core region · CPC title

• H04N25/73

  using interline transfer [IT] · CPC title

• H10D84/891

  characterised by the integration of only components covered by H10D44/00, e.g. integration of charge-coupled devices [CCD] or charge injection devices [CID · CPC title

• H10B99/22

  including field-effect components · CPC title