Semiconductor device, electronic device, and authentication system

Patent metadata

Field	Value
Publication number	US-10109633-B2
Application number	US-201715490383-A
Country	US
Kind code	B2
Filing date	Apr 18, 2017
Priority date	Apr 27, 2016
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

A novel semiconductor device is provided. A memory cell MC has a function of supplying a signal corresponding to the product of first data and second data to a wiring BX, and also has a function of supplying a signal corresponding to the product of the first data and third data to a wiring BY. The wiring BX is connected to a plurality of memory cells MC. Each of the plurality of memory cells MC outputs a signal corresponding to the result of the product operation to the wiring BX. The wiring BX has a function of transmitting a signal corresponding to the sum of these signals. The wiring BY is connected to a plurality of memory cells MC. Each of the plurality of memory cells MC outputs a signal corresponding to the result of the product operation to the wiring BY. The wiring BY has a function of transmitting a signal corresponding to the sum of these signals.

First claim

What is claimed is:

1. A semiconductor device comprising:
a memory cell,
wherein the memory cell comprises a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor,
wherein a gate of the first transistor is electrically connected to a first wiring,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, a gate of the third transistor, one electrode of the first capacitor, and one electrode of the second capacitor,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a fourth wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a fifth wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to the fourth wiring,
wherein the other electrode of the first capacitor is electrically connected to a sixth wiring, and
wherein the other electrode of the second capacitor is electrically connected to a seventh wiring.

2. The semiconductor device according to claim 1 ,
wherein the memory cell is configured to hold a first potential,
wherein the sixth wiring is configured to supply a second potential to the memory cell,
wherein the seventh wiring is configured to supply a third potential to the memory cell,
wherein a first current corresponding to a fourth potential is supplied between the memory cell and the third wiring,
wherein the fourth potential corresponds to the product of the first potential and the second potential,
wherein a second current corresponding to a fifth potential is supplied between the memory cell and the fifth wiring, and
wherein the fifth potential corresponds to the product of the first potential and the third potential.

3. The semiconductor device according to claim 2 , wherein the first potential, the second potential, and the third potential are each an analog potential.

4. The semiconductor device according to claim 1 , wherein the first transistor comprises an oxide semiconductor in a channel formation region.

5. An electronic device comprising:
the semiconductor device according to claim 1 ; and
at least one of a display portion, an operation key, a speaker, and a microphone.

6. An authentication system comprising:
an identification portion comprising the semiconductor device according to claim 1 ,
wherein the identification portion is configured to receive a signal corresponding to a character, a figure, a symbol, or voice sensed by a sensor portion of an electronic device and is configured to identify the signal, and
wherein an identification result is transmitted from the identification portion to a control portion configured to control an operation of the electronic device.

7. A semiconductor device comprising:
a plurality of memory cells comprising at least a first memory cell, a second memory cell, and a third memory cell,
wherein the first memory cell comprises a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor,
wherein a gate of the first transistor is electrically connected to a first wiring,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, a gate of the third transistor, one electrode of the first capacitor, and one electrode of the second capacitor,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a fourth wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a fifth wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to the fourth wiring,
wherein the other electrode of the first capacitor is electrically connected to a sixth wiring, and
wherein the other electrode of the second capacitor is electrically connected to a seventh wiring.

8. The semiconductor device according to claim 7 ,
wherein the first memory cell is configured to hold a first potential,
wherein the sixth wiring is configured to supply a second potential to the first memory cell,
wherein the seventh wiring is configured to supply a third potential to the first memory cell,
wherein a first current corresponding to a fourth potential is supplied between the first memory cell and the third wiring,
wherein the fourth potential corresponds to the product of the first potential and the second potential,
wherein a second current corresponding to a fifth potential is supplied between the first memory cell and the fifth wiring, and
wherein the fifth potential corresponds to the product of the first potential and the third potential.

9. The semiconductor device according to claim 8 , wherein the first potential, the second potential, and the third potential are each an analog potential.

10. The semiconductor device according to claim 8 ,
wherein the first memory cell and the second memory cell are electrically connected to the third wiring and the seventh wiring,
wherein the first memory cell and the third memory cell are electrically connected to the fifth wiring and the sixth wiring,
wherein a third current corresponding to the sum of the fourth potential of the first memory cell and the fourth potential of the second memory cell is supplied to the third wiring, and
wherein a fourth current corresponding to the sum of the fifth potential of the first memory cell and the fifth potential of the third memory cell is supplied to the fifth wiring.

11. The semiconductor device according to claim 7 , wherein the first transistor comprises an oxide semiconductor in a channel formation region.

12. The semiconductor device according to claim 7 , wherein each of the second memory cell and the third memory cell comprises a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor.

13. The semiconductor device according to claim 12 , wherein the first transistor comprises an oxide semiconductor in a channel formation region.

14. An electronic device comprising:
the semiconductor device according to claim 7 ; and
at least one of a display portion, an operation key, a speaker, and a microphone.

15. An authentication system comprising:
an identification portion comprising the semiconductor device according to claim 7 ,
wherein the identification portion is configured to receive a signal corresponding to a character, a figure, a symbol, or voice sensed by a sensor portion of an electronic device and is configured to identify the signal, and
wherein an identification result is transmitted from the identification portion to a control portion configured to control an operation of the electronic device.

Assignees

• Semiconductor Energy Lab

Inventors

• Kurokawa Yoshiyuki

Classifications

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• H01L29/7869

  Electricity · mapped topic

• H01L27/105 Primary

  Electricity · mapped topic

• H01L27/1052

  Electricity · mapped topic

• G11C11/401

  forming cells needing refreshing or charge regeneration, i.e. dynamic cells · CPC title