Capacitive discharge programming for two-terminal memory cells

Patent metadata

Field	Value
Publication number	US-8934280-B1
Application number	US-201313761132-A
Country	US
Kind code	B1
Filing date	Feb 6, 2013
Priority date	Feb 6, 2013
Publication date	Jan 13, 2015
Grant date	Jan 13, 2015

Abstract

Providing for capacitive programming of two-terminal memory devices is described herein. By way of example, a capacitance circuit can be precharged to a predetermined program voltage to facilitate programming one or more memory cells. The capacitance circuit can be disconnected from a power source and connected instead to the memory cell(s), enabling charge stored by the capacitance circuit to discharge through the memory cell(s). A current at the memory cell(s) can program the cell, while a total amount of discharge is limited to the charge stored by the capacitance circuit. Limiting the total charge can serve to also limit joule heating of the target memory cell, power consumption of a memory device, as well as other benefits.

First claim

What is claimed is:

1. A method for programming a two-terminal memory cell, comprising:
coupling a power source to a capacitor and precharging the capacitor to a programming voltage;
decoupling the power source from the capacitor when the capacitor has been precharged to the programming voltage; thereafter
selecting a two-terminal memory cell and connecting the capacitor that has been precharged to the programming voltage to a program terminal of the two-terminal memory cell;
coupling a second terminal of the two-terminal memory cell to ground;
controlling a magnitude of current flowing through the two-terminal memory cell in conjunction with the programming; and
terminating discharging of the charge stored by the capacitance of the bitline in response to a change in program state of the two-terminal memory cell, change in voltage.

2. The method of claim 1 , further comprising determining the change in program state of the two-terminal memory cell with a voltage detection circuit.

3. The method of claim 1 , further comprising selecting the programming voltage at least in part based on at least one of: a capacitance value of the capacitor, a desired amount of charge for the capacitor or the magnitude of the controlled current.

4. The method of claim 3 , wherein selecting the programming voltage is further based on a magnitude of current associated with a change of state of the two-terminal memory cell from one resistance state to a different resistance state.

5. The method of claim 1 , wherein precharging the capacitor further comprises precharging an internal or external capacitor in conjunction with a global bitline of a memory device associated with the two-terminal memory cell, a capacitance value of the capacitor comprising a parasitic capacitance associated with the bitline plus a capacitance of the internal or external capacitor.

6. The method of claim 1 , further comprising inhibiting discharge of the capacitor beyond a predetermined drop in voltage at the capacitor.

7. The method of claim 1 , further comprising coupling the capacitor to the two-terminal memory cell to an inhibit bias in response to terminating the discharging.

8. The method of claim 1 , wherein discharging at least the portion of charge further comprises closing a switch between the capacitor and a local bitline on which the two-terminal memory cell is coupled.

9. The method of claim 1 , wherein discharging at least the portion of charge further comprises closing a switch between a global bitline of a memory cell serving at least in part as the capacitor and a local bitline associated with a sector of the memory device in which the two-terminal memory cell resides.

10. The method of claim 9 , wherein closing the switch between the global bitline and the local bitline further comprises opening a switch between the power source and the global bitline.

11. The method of claim 9 , further comprising opening the switch between the bitline and the local bitline in response to precharging the local bitline to the programming voltage.

12. The method of claim 11 , wherein connecting the second terminal of the two-terminal memory cell to ground further comprises grounding a wordline connected to the second terminal.

13. The method of claim 1 , further comprising activating a wordline of the two-terminal memory cell to facilitate the discharging at least the portion of charge, and floating or inhibiting a local bitline connected to a second two-terminal memory cell on the wordline, to facilitate inhibiting programming of the second two-terminal memory cell.

14. The method of claim 1 , further comprising activating a wordline of a memory device connected to the two-terminal memory cell and connected to a second two-terminal memory cell, and connecting respective local bitlines of the memory device to the capacitance, wherein the respective local bitlines are connected respectively to the two-terminal memory cell and to the second two-terminal memory cell, and further wherein discharging at least the portion of charge comprises discharging similar portions of the charge stored by the capacitor through the two-terminal memory cell and the second two-terminal memory cell to facilitate concurrent programming of multiple two-terminal memory cells.

15. The method of claim 14 , further comprising selecting a value of the programming voltage or an amount of charge for precharging the bitline at least in part based on a number of the multiple two-terminal memory cells.

16. A semiconductor memory device, comprising:
a power source configured to generate and output a selected voltage within a predetermined range of voltages;
a global bitline and a wordline, the bitline having an associated bitline capacitance value;
a two-terminal memory cell connected at one terminal to the wordline and connected at a second terminal to a local bitline,
a select transistor configured to electrically connect or electrically isolate the two-terminal memory cell and the local bitline from the global bitline in response to activation or deactivation of the select transistor; and
a program control circuit configured to set the selected voltage to a program voltage value; precharge the global bitline to the program voltage value and initiate discharging the precharged global bitline through the two-terminal memory cell to facilitate programming the two-terminal memory cell;
a current inhibitor circuit configured to limit a current through the two-terminal memory cell in response to the discharging; and
a charge preservation circuit configured to identify a change in program state of the two-terminal memory cell, and to terminate the discharging in response to identifying the change in program state.

17. The semiconductor memory device of claim 16 , the two-terminal memory cell comprising a resistive random access memory, a phase-change random access memory, a magnetoresistive random access memory, or a ferroelectric random access memory.

18. The semiconductor memory device of claim 16 , wherein the program control circuit is further configured to open the select transistor in conjunction with precharging the global bitline to the program voltage, electrically isolate the global bitline from the power source following the precharging the bitline to the program voltage, and closing the select transistor to electrically connect the global bitline to the two-terminal memory cell to facilitate the discharging at least a portion of stored charge from the bitline to the two-terminal memory cell in conjunction with the facilitating programming the two-terminal memory cell.

19. A memory circuit, comprising:
an electrical switch that selectively connects and disconnects a voltage supply to a capacitance circuit comprising a global bitline connected to a capacitor;
a set of second electrical switches that, respectively, selectively connect and disconnect the capacitance circuit to respective ones of a set of local bitlines associated with memory cells of the memory circuit;
a control circuit configured to charge the capacitance circuit and the set of local bitlines and limit an amount of charge consumed in programming the memory cells to a maximum charge, wherein:
the control circuit:
closes the electrical switch in response to initiation of a program operation;
charges the capacitance circuit;
opens the electrical switch in response to charging the capacitance circuit and closes at least one of the set of second electrical switches to charge a plurality of the set of local bitlines from the capacitance ci

Assignees

• Crossbar Inc

Inventors

• Kuo Harry
• Nazarian Hagop
• Nguyen San Thanh

Classifications

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title