Capacitor integrated with a transistor for logic and memory applications

Patent metadata

Field	Value
Publication number	US-12274071-B1
Application number	US-202318326424-A
Country	US
Kind code	B1
Filing date	May 31, 2023
Priority date	Feb 10, 2023
Publication date	Apr 8, 2025
Grant date	Apr 8, 2025

Abstract

A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.

First claim

What is claimed is:

1. A device comprising:
a transistor above a substrate;
an electrode structure coupled with a terminal of the transistor;
a plate electrode coupled with the electrode structure, the plate electrode comprising at least a first conductive layer and a second conductive layer on the first conductive layer and wherein the first conductive layer is part of a first die, and the second conductive layer is part of a second die; and
a planar capacitor comprising a non-linear polar dielectric material having a form ABO X , wherein A and B are two different cations, and wherein X is 1, 2, or 3.

2. The device of claim 1 , wherein the non-linear polar dielectric material comprises one of:
a perovskite material which includes one of: BaTiO 3 , KNbO 3 , or NaTaO 3 ;
lead zirconium titanate (PZT) or PZT;
bismuth ferrite (BFO);
a relaxor ferroelectric material which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a hexagonal ferroelectric which includes one of: YMnO 3 or LuFeO 3 ;
hexagonal ferroelectrics of a type h-RMnO 3 , wherein R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides or their alloyed oxides;
hafnium oxide of a form Hf 1-x E x O z , where ‘x’ is a fraction, and E includes one of Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y;
Al (1-x) Sc (x) N, Ga (1-x) Sc (x) N, Al (1-x) Y (x) N or Al (a) Mg (b) Nb (c) N, wherein a, b, and c are respective compositional fractions;
niobate type compounds including LiNbO 3 , LiTaO 3 , LiTaO 2 F 2 , Sr x Ba 1-x Nb 2 O 6 where 0.32≤x≤0.8 or KSr 2 Nb 5 O 15 ;
an improper ferroelectric material which comprises an epitaxial bilayer stack including one of: [barium titanate/strontium titanate] n or [lanthanum aluminate/strontium titanate] n, wherein ‘n’ represents a number of bilayers, and wherein ‘n’ is between 1 and 100; or
a paraelectric material that comprises SrTiO 3 , Ba(x)Sr(y)TiO 3 , HfZrO 2 , or Hf—Si—O, or a PMN-PT based relaxor ferroelectrics.

3. The device of claim 2 , wherein at least A is combined with an A site dopant, wherein the A site dopant comprises an element from lanthanide series of periodic table, wherein B is combined with a dopant, and wherein the dopant is a B site dopant and comprises an element from 3d, 4d, 5d, 6d, 4f, or 5f series of periodic table.

4. The device of claim 1 , wherein the first conductive layer comprises first refractory metals or nitrides of the first refractory metals and the second conductive layer comprises second refractory metals or nitrides of the second refractory metals.

5. The device of claim 1 , wherein the first conductive layer comprises a first grain configuration and wherein the second conductive layer comprises a second grain configuration.

6. The device of claim 5 , wherein the first grain configuration comprises a first columnar structure, wherein the second grain configuration comprises second columnar structure, and wherein the first grain configuration and the second grain configuration are misaligned.

7. The device of claim 6 , wherein the first columnar structure is at a first angle and wherein the second columnar structure is at a second angle.

8. The device of claim 1 , wherein the first conductive layer comprises first zone with a first grain structure and a second zone with a second grain structure, wherein the second zone is above the first zone, wherein the first grain structure has a higher density of grains than the second grain structure, wherein the second conductive layer comprises a third zone with a third grain structure and a fourth zone with a fourth grain structure, wherein the fourth zone is above the third zone, and wherein the fourth grain structure has a higher density of grains than the third grain structure.

9. The device of claim 1 , wherein oxygen is present at an interface between the first conductive layer and the second conductive layer.

10. The device of claim 1 , wherein the first conductive layer is amorphous or polycrystalline, and the second conductive layer is amorphous or polycrystalline.

11. The device of claim 1 , wherein an interface between the first conductive layer and the second conductive layer comprises one or more voids, and wherein the one or more voids have a length that is less than 1 nm.

12. The device of claim 1 further comprising a dielectric spacer, the dielectric spacer comprising a first sidewall adjacent to a second sidewall of the planar capacitor, wherein the first sidewall is aligned with a third sidewall of the plate electrode.

13. A system comprising:
a first conductive layer of a first substrate in contact with a second conductive layer of second substrate, wherein the first conductive layer is a first terminal of a capacitor comprising a non-linear polar dielectric material having a form ABO X , wherein A and B are two different cations, and wherein X is 1, 2, or 3, and wherein the second conductive layer is coupled with a terminal of a transistor.

14. The system of claim 13 , wherein the first conductive layer comprises refractory metals or nitrides of refractory metals and the second conductive layer comprises refractory metals or nitrides of refractory metals and wherein the non-linear polar dielectric material comprises one of:
a perovskite material which includes one of: BaTiO 3 , KNbO 3 , or NaTaO 3 ;
lead zirconium titanate (PZT) or PZT;
bismuth ferrite (BFO);
a relaxor ferroelectric material which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a hexagonal ferroelectric which includes one of: YMnO 3 or LuFeO 3 ;
hexagonal ferroelectrics of a type h-RMnO 3 , wherein R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides or their alloyed oxides;
hafnium oxide of a form Hf 1-x E x O z , where ‘x’ is a fraction, and E includes one of Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y;
Al (1-x) Sc (x) N, Ga (1-x) Sc (x) N, Al (1-x) Y (x) N or Al (a) Mg (b) Nb (c) N, wherein a, b, and c are respective compositional fractions;
niobate type compounds including LiNbO 3 , LiTaO 3 , LiTaO 2 F 2 , Sr x Ba 1-x Nb 2 O 6 where 0.32≤x≤0.8 or KSr 2 Nb 5 O 15 ;
an improper ferroelectric material which comprises an epitaxial bilayer stack including one of: [barium titanate/strontium titanate] n or [lanthanum aluminate/strontium titanate]n, wherein ‘n’ represents a number of bilayers, and wherein ‘n’ is between 1 and 100; or
a paraelectric material that comprises SrTiO 3 , Ba(x)Sr(y)TiO 3 , HfZrO 2 , or Hf—Si—O, or a PMN-PT based relaxor ferroelectrics, and wherein B is combined with a dopant, wherein the dopant is a B site dopant and co

Assignees

• Kepler Computing Inc

Inventors

• Manfrini Mauricio
• Sato Noriyuki
• Clarkson James David
• Fernandez Abel
• Rathi Somilkumar J
• Mukherjee Niloy
• Gosavi Tanay
• Mathuriya Amrita
• Dokania Rajeev Kumar
• Manipatruni Sasikanth

Classifications

• H10B53/30 Primary

  characterised by the memory core region · CPC title