Circuit and method for creating additional data transitions

Patent metadata

Field	Value
Publication number	US-9973329-B2
Application number	US-201715474593-A
Country	US
Kind code	B2
Filing date	Mar 30, 2017
Priority date	Sep 18, 2015
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

When a data path includes CMOS circuitry, such circuitry may introduce jitter into the data signal. Embodiments are described in which additional data transitions are made to occur, and these additional data transitions may change the characteristics of the data frequency content transferred to the power supply so that such noise may be better filtered. This may have an effect of reducing jitter in the data signal. In one embodiment, a second data signal is generated to be a version of a first data signal with every second bit inverted. Second CMOS circuitry receives the second data signal in parallel to first CMOS circuitry receiving the first data signal. The first CMOS circuitry and the second CMOS circuitry are connected to a same power supply.

First claim

The invention claimed is:

1. A transmitter comprising:
first CMOS circuitry to receive a first data signal representing a plurality of bits;
a signal generating circuit to generate a second data signal so that the second data signal is a version of the first data signal with every second bit of the plurality of bits inverted; and
second CMOS circuitry to receive the second data signal in parallel to the first CMOS circuitry receiving the first data signal to result in a data transition in either the first CMOS circuitry or the second CMOS circuitry every bit period for the plurality of bits,
wherein the first CMOS circuitry and the second CMOS circuitry are connected to a same power supply.

2. The transmitter of claim 1 , wherein the transmitter is part of a serializer/deserializer (SERDES).

3. The transmitter of claim 1 , wherein the transmitter is part of a serializer.

4. The transmitter of claim 1 , wherein the second CMOS circuitry is substantially the same as the first CMOS circuitry.

5. The transmitter of claim 4 , further comprising:
a first multiplexer to multiplex a pair of half-rate data signals to produce the first data signal; and
wherein the signal generating circuit comprises:
an inverter to invert one of the pair of half-rate data signals to produce an inverted half-rate data signal, and
a second multiplexer to multiplex the inverted half-rate data signal with the other one of the pair of half-rate data signals to produce the second data signal.

6. The transmitter of claim 5 , wherein the same power supply is a first power supply, and wherein the transmitter further comprises:
third CMOS circuitry to output the pair of half-rate data signals, the third CMOS circuitry connected to a second power supply and not connected to the first power supply.

7. The transmitter of claim 6 , further comprising:
fourth CMOS circuitry to output a clock used to select an input line of at least the first multiplexer, the fourth CMOS circuitry connected to a third power supply and not connected to the first power supply or the second power supply.

8. The transmitter of claim 1 , further comprising:
a capacitor that creates a filter to filter data frequency content, the data frequency content being made more narrowband by having the data transition in either the first CMOS circuitry or the second CMOS circuitry every bit period for the plurality of bits.

9. The transmitter of claim 4 , wherein the first CMOS circuitry comprises:
a plurality of CMOS gates connected in series to perform drive amplification of the first data signal; and
wherein the second CMOS circuitry comprises:
a copy of the plurality of CMOS gates connected in series to perform drive amplification of the second data signal.

10. The transmitter of claim 1 , wherein the signal generating circuit comprises:
an exclusive-or (XOR) logic gate to receive as an input the first data signal and a clock, and to produce as an output the second data signal equal to an XOR of the first data signal and the clock; or
a multiplexer to receive as an input the first data signal in differential form D in and D in , and to output the second data signal by alternately selecting between D in and D in .

11. The transmitter of claim 1 , further comprising:
a first multiplexer to multiplex four quarter-rate data signals to produce the first data signal; and
wherein the signal generating circuit comprises:
an inverter to invert one of the quarter-rate data signals to produce a first inverted quarter-rate data signal;
another inverter to invert another one of the quarter-rate data signals to produce a second inverted quarter-rate data signal; and
a second multiplexer to produce the second data signal by multiplexing the first inverted quarter-rate data signal, the second inverted quarter-rate data signal, and the remaining other two quarter-rate data signals that were not inverted.

12. A system comprising:
a first multiplexer to multiplex a pair of half-rate data signals to produce a first full-rate data signal;
first CMOS circuitry to receive the first full-rate data signal;
an inverter to invert one of the pair of half-rate data signals to produce an inverted half-rate data signal, and a second multiplexer to multiplex the inverted half-rate data signal with the other one of the pair of half-rate data signals to produce a second full-rate data signal; and
second CMOS circuitry to receive the second full-rate data signal in parallel to the first CMOS circuitry receiving the first full-rate data signal to result in a data transition in either the first CMOS circuitry or the second CMOS circuitry every bit period, the first CMOS circuitry and the second CMOS circuitry being connected to a same power supply, and the second CMOS circuitry being substantially the same as the first CMOS circuitry,
wherein the system is part of: a serialize/deserialize (SERDES) receiver or transmitter, or an advanced modulation receiver or transmitter, or a clock/data recover (CDR) device, or a CMOS transimpedance amplifier (TIA) circuit, or a CMOS laser driver, or an analog to digital converter (ADC) circuit.

13. The system of claim 12 wherein the first CMOS circuitry comprises a plurality of CMOS gates connected in series to perform drive amplification of the first full-rate data signal, and the second CMOS circuitry comprises a copy of the first CMOS circuitry to perform drive amplification of the second full-rate data signal.

14. A method in a transmitter, the method comprising:
receiving a first data signal representing a plurality of bits at first CMOS circuitry;
generating a second data signal so that the second data signal is a version of the first data signal with every second bit of the plurality of bits inverted; and
receiving the second data signal at second CMOS circuitry in parallel to receiving the first data signal at the first CMOS circuitry to result in a data transition in either the first CMOS circuitry or the second CMOS circuitry every bit period for the plurality of bits, the first CMOS circuitry and the second CMOS circuitry being connected to a same power supply.

15. The method of claim 14 , wherein the transmitter is part of a serializer/deserializer (SERDES).

16. The method of claim 14 , wherein the transmitter is part of a serializer.

17. The method of claim 14 , wherein the second CMOS circuitry is substantially the same as the first CMOS circuitry.

18. The method of claim 17 , further comprising:
multiplexing a pair of half-rate data signals to produce the first data signal; and
wherein generating the second data signal comprises:
inverting one of the pair of half-rate data signals to produce an inverted half-rate data signal; and
multiplexing the inverted half-rate data signal with the other one of the pair of half-rate data signals to produce the second data signal.

19. The method of claim 14 further comprising:
filtering data frequency content that is made more narrowband by having the data transition in either the first CMOS circuitry or the second CMOS circuitry every bit period for the plurality of bits.

20. The method of claim 14 , wherein the first CMOS circuitry and the second CMOS circuitry each comprise a plurality of CMOS gates connected in series, and wherein the method further comprises:
performing drive amplification of the first data signal in the first CMOS circuitry; and
performing drive amplification of the second data signal in the second CMOS circuitry.

Assignees

• Inphi Corp

Inventors

• Hood Sheldon James
• Banens Paul Thomas

Classifications

• H04L7/0016 Primary

  correction of synchronization errors · CPC title

• H03L7/0807

  concerning mainly a recovery circuit for the reference signal · CPC title

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H04B1/04

  Circuits · CPC title

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title