Method for manufacturing semiconductor device and semiconductor device
US-9478545-B2 · Oct 25, 2016 · US
Method for manufacturing semiconductor device and semiconductor device
US9748244B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9748244-B2 |
| Application number | US-201615266091-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 15, 2016 |
| Priority date | Dec 19, 2011 |
| Publication date | Aug 29, 2017 |
| Grant date | Aug 29, 2017 |
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- Title
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Abstract
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A semiconductor device includes a first and second fin-shaped semiconductor layers on a substrate. A first insulating film is around the first and second fin-shaped layers. A first and second pillar-shaped semiconductor layers reside on the first and second fin-shaped layers, respectively. A width of a bottom of the first pillar-shaped semiconductor layer is equal to a width of a top of the first fin-shaped semiconductor layer, and a width of a bottom of the second pillar-shaped semiconductor layer is equal to the width of a top of the second fin-shaped semiconductor layer. First and second gate insulating films and first and second metal gate electrodes reside around the first and second pillar-shaped layers, respectively. A metal gate line is connected to the first and second metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped layers.
First claim
Opening claim text (preview).
The invention claimed is: 1. A semiconductor device comprising: a first fin-shaped semiconductor layer on a substrate; a second fin-shaped semiconductor layer on the substrate; a first insulating film around the first fin-shaped semiconductor layer and the second fin-shaped semiconductor layer; a first pillar-shaped semiconductor layer on the first fin-shaped semiconductor layer; a second pillar-shaped semiconductor layer on the second fin-shaped semiconductor layer, where a width of a bottom of the first pillar-shaped semiconductor layer is equal to a width of a top of the first fin-shaped semiconductor layer and a width of a bottom of the second pillar-shaped semiconductor layer is equal to the width of a top of the second fin-shaped semiconductor layer; an n-type diffusion layer in an upper portion of the first fin-shaped semiconductor layer; a p-type diffusion layer in an upper portion of the second fin-shaped semiconductor layer; a first gate insulating film around the first pillar-shaped semiconductor layer; a first metal gate electrode around the first gate insulating film; a second gate insulating film around the second pillar-shaped semiconductor layer; a second metal gate electrode around the second gate insulating film; and a metal gate line connected to the first metal gate electrode and the second metal gate electrode and extending in a direction perpendicular to the first fin-shaped semiconductor layer and the second fin-shaped semiconductor layer.
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9748244B2 cover?
- A semiconductor device includes a first and second fin-shaped semiconductor layers on a substrate. A first insulating film is around the first and second fin-shaped layers. A first and second pillar-shaped semiconductor layers reside on the first and second fin-shaped layers, respectively. A width of a bottom of the first pillar-shaped semiconductor layer is equal to a width of a top of the fir…
- Who is the assignee on this patent?
- Unisantis Elect Singapore Pte
- What technology area does this patent fall under?
- Primary CPC classification H01L27/0924. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 29 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).