Memory device including vertical stack structure, method of fabricating the same, and electronic device including memory device

Patent metadata

Field	Value
Publication number	US-12268009-B2
Application number	US-202217685942-A
Country	US
Kind code	B2
Filing date	Mar 3, 2022
Priority date	Sep 24, 2021
Publication date	Apr 1, 2025
Grant date	Apr 1, 2025

Abstract

Disclosed are a memory device including a vertical stack structure, a method of manufacturing the same, and/or an electronic device including the memory device. The memory device including a vertical stack structure includes an oxygen scavenger layer on a base substrate, a recording material layer on the oxygen scavenger layer and in direct contact with the oxygen scavenger layer, a channel layer on the recording material layer, a gate insulating layer on the channel layer, and a gate electrode on the gate insulating layer. The oxygen scavenger layer includes an element that forms oxygen vacancies in the recording material layer and does not include oxygen.

First claim

What is claimed is:

1. A memory device comprising:
a base substrate;
an oxygen scavenger layer on the base substrate;
a recording material layer on the oxygen scavenger layer, the recording material layer being in direct contact with the oxygen scavenger layer;
a channel layer on the recording material layer;
a gate insulating layer on the channel layer; and
a gate electrode on the gate insulating layer,
wherein the oxygen scavenger layer comprises an element that forms oxygen vacancies in the recording material layer and does not comprise oxygen.

2. The memory device of claim 1 , wherein the base substrate and the oxygen scavenger layer include a same material and correspond to one layer.

3. The memory device of claim 2 , wherein the base substrate and the oxygen scavenger layer include semiconductor layers.

4. The memory device of claim 3 , wherein the semiconductor layers include undoped semiconductor layers.

5. The memory device of claim 3 , wherein the semiconductor layers include semiconductor layers doped with a dopant, and insulating layers are at both ends of the doped semiconductor layers.

6. The memory device of claim 2 , wherein the base substrate and the oxygen scavenger layer include metal layers, and insulating layers are at both ends of the metal layers.

7. The memory device of claim 1 , wherein the oxygen scavenger layer incudes a semiconductor layer doped with a dopant, and insulating layers are at both ends of the semiconductor layer.

8. The memory device of claim 1 , wherein the oxygen scavenger layer comprises a metal layer, and insulating layers are at both ends of the metal layer.

9. The memory device of claim 1 , wherein the element is a semiconductor element.

10. The memory device of claim 9 , wherein the oxygen scavenger layer further comprises nitrogen (N).

11. The memory device of claim 1 , wherein the oxygen scavenger layer comprises:
a first sub-material layer on the base substrate; and
a second sub-material layer on the first sub-material layer and in direct contact with the recording material layer.

12. The memory device of claim 11 , wherein one of the first and second sub-material layers includes a layer comprising a semiconductor component, and the other one of the first and second sub-material layers includes a metal layer.

13. The memory device of claim 11 , wherein one of the first and second sub-material layers includes a semiconductor layer, and the other one of the first and second sub-material layers includes a nitride layer.

14. The memory device of claim 12 , wherein the layer comprising the semiconductor component comprises nitrogen.

15. The memory device of claim 13 , wherein the semiconductor layer includes a silicon layer doped with a dopant, or includes an undoped silicon layer.

16. The memory device of claim 11 , wherein one of the first and second sub-material layers includes a semiconductor layer doped with a dopant, and the other one of the first and second sub-material layers includes an undoped semiconductor layer.

17. The memory device of claim 1 , wherein the base substrate includes an insulating structure comprising oxygen, and the oxygen scavenger layer includes a barrier configured to prevent movement of oxygen of the base substrate to the recording material layer.

18. The memory device of claim 1 , wherein a plurality of gate electrodes are aligned on the gate insulating layer in a first direction, and isolation layers are between the plurality of the gate electrodes and insulate the plurality of the gate electrodes from each other.

19. The memory device of claim 18 , wherein the base substrate has a cylindrical shape parallel to the first direction, and
the oxygen scavenger layer, the recording material layer, the channel layer, and the gate insulating layer are sequentially stacked on a cylindrical surface of the base substrate to surround the base substrate.

20. The memory device of claim 19 , wherein the base substrate, the oxygen scavenger layer, the recording material layer, the channel layer, the gate insulating layer, the gate electrodes, and the isolation layers are on a substrate comprising a doping region,
a stack comprising the base substrate, the oxygen scavenger layer, the recording material layer, the channel layer, the gate insulating layer, and the channel layer is perpendicular to a surface of the substrate and has one end of the stack in contact with the doping region, and
the gate electrodes and the isolation layers are in parallel to the substrate and surround the stack.

21. The memory device of claim 20 , wherein the other end of the stack opposite to the one end of the stack is in contact with a drain region, and a bit line is connected to the drain region.

22. The memory device of claim 1 , wherein the recording material layer comprises at least one of a variable resistance material and a phase change material.

23. An electronic device comprising the memory device of claim 1 .

24. An electronic device comprising:
an oxygen scavenger layer;
a recording material layer on the oxygen scavenger layer, the recording material layer directly contacting the oxygen scavenger layer; and
a channel layer on the recording material layer,
wherein the oxygen scavenger layer comprises an element that creates oxygen vacancies in the recording material layer in response to voltages applied to the channel layer, and does not comprise oxygen.

25. The electronic device of claim 24 , wherein the oxygen scavenger layer serves as an insulating substrate.

26. The electronic device of claim 24 , wherein a thickness of the oxygen scavenger layer is between 30 nm and 70 nm.

27. The electronic device of claim 26 , wherein the thickness of the oxygen scavenger layer is about 50 nm.

28. The electronic device of claim 24 , further comprising:
a gate electrode layer on the channel layer; and
a source electrode on the channel layer,
wherein the oxygen scavenger layer is configured to create oxygen vacancies in the recording material layer in response to a voltage applied to the gate electrode layer or to the source electrode.

29. A method of fabricating a memory device, the method comprising:
forming a stack structure by alternately and repeatedly depositing sacrificial layers and isolation layers on a substrate;
forming a channel hole penetrating the stack structure;
sequentially forming a gate insulating layer, a channel layer, a recording material layer, and an oxygen scavenger layer on an inner surface of the channel hole;
filling, with a buried material, an inner space of the channel hole remaining after the oxygen scavenger layer is formed;
forming gate holes by removing the sacrificial layers; and
depositing an electrode material in the gate holes,
wherein the oxygen scavenger layer comprises an element that forms oxygen vacancies in the recording material layer and does not comprise oxygen.

30. The method of claim 29 , further comprising, after the forming of the gate insulating layer and the channel layer on the inner surface of the channel hole and before the forming of the recording material layer, removing an insulating material and a channel material that are deposited on a bottom surface of the channel hole.

31. The method of claim 29 , wherein the oxygen scavenger layer and the buried material are

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Yumin
• Kim Doyoon
• Kim Seyun
• Song Hyunjae
• Yang Seungyeul

Classifications

• H10N70/881

  Switching materials · CPC title

• H10N70/8833

  Binary metal oxides, e.g. TaOx · CPC title

• H10N70/8265

  on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices · CPC title

• H10N70/24

  based on migration or redistribution of ionic species, e.g. anions, vacancies · CPC title

• H10B63/84

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title