Integrated circuit device

Patent metadata

Field	Value
Publication number	US-12249606-B2
Application number	US-202418414039-A
Country	US
Kind code	B2
Filing date	Jan 16, 2024
Priority date	Aug 12, 2020
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.

First claim

What is claimed is:

1. A method of manufacturing an integrated circuit device, the method comprising:
forming a structure including a fin-type active region and a pair of nanosheet stacks, the fin-type active region extending lengthwise in a first horizontal direction, each of the pair of nanosheet stacks including a plurality of nanosheets which overlap each other in a vertical direction on a fin top of the fin-type active region; and
forming a source/drain area between the pair of nanosheet stacks on the fin-type active region, the forming of the source/drain area comprising:
forming an outer blocking layer;
forming an inner blocking layer on the outer blocking layer; and
forming a main body layer on the inner blocking layer,
wherein each of the outer blocking layer and the main body layer includes a Si 1-x Ge x layer, where x≠0, and the inner blocking layer includes a Si layer, and
wherein the inner blocking layer has a width greater than a width of the outer blocking layer.

2. The method of claim 1 , wherein in the forming the source/drain area, the inner blocking layer includes an undoped Si layer.

3. The method of claim 1 , wherein in the forming the source/drain area, the inner blocking layer includes a Si layer doped with a p-type dopant, the p-type dopant being boron (B) or gallium (Ga).

4. The method of claim 1 , further comprising:
after the forming of the source/drain area, forming a gate structure comprising a main gate portion extending in a second horizontal direction intersecting the first horizontal direction on the plurality of nanosheets and a plurality of sub-gate portions integrally connected to the main gate portion, the plurality of sub-gate portions being arranged one by one between the plurality of nanosheets on the fin-type active region.

5. The method of claim 1 , wherein the forming of the source/drain area comprises performing a selective epitaxial growth (SEG) process to sequentially form the outer blocking layer, the inner blocking layer, and the main body layer, and
wherein the inner blocking layer is spaced apart from the nanosheet stack with the outer blocking layer therebetween.

6. The method of claim 1 , wherein in the forming of the structure, each of the pair of nanosheet stacks further includes a plurality of sacrificial semiconductor layers, the plurality of sacrificial semiconductor layers and the plurality of nanosheets being alternately stacked on the fin-type active region one by one, and
wherein in the forming of the outer blocking layer, a width of a portion of the outer blocking layer covering each of the plurality of sacrificial semiconductor layers in the first horizontal direction is less than ⅕ of a maximum width of the source/drain area in the first horizontal direction.

7. The method of claim 1 , wherein in the forming of the structure, each of the pair of nanosheet stacks further includes a plurality of sacrificial semiconductor layers, the plurality of sacrificial semiconductor layers and the plurality of nanosheets being alternately stacked on the fin-type active region one by one, and
wherein in the forming of the inner blocking layer, a width of a portion of the inner blocking layer covering each of the plurality of sacrificial semiconductor layers in the first horizontal direction is less than ⅕ of a maximum width of the source/drain area in the first horizontal direction.

8. The method of claim 1 , wherein the forming of the source/drain area further comprises forming a capping layer on the main body layer,
wherein the capping layer is spaced apart from the inner blocking layer, and
wherein the capping layer includes an undoped Si layer or a Si layer doped with a p-type dopant.

9. The method of claim 1 , wherein in the forming of the source/drain area, a level of a lowermost surface of the source/drain area is lower than a level of the fin top of the fin-type active region in the vertical direction.

10. The method of claim 1 , wherein in the forming of the outer blocking layer, the outer blocking layer is formed to include a first bottom portion contacting the fin-type active area, the first bottom portion having a first thickness in the vertical direction, and
wherein in the forming of the inner blocking layer, the inner blocking layer is formed to include a second bottom portion contacting the first bottom portion of the outer blocking layer, the second bottom portion having a second thickness in the vertical direction, and the second thickness being equal to or greater than the first thickness.

11. The method of claim 1 , wherein in the forming of the outer blocking layer, the outer blocking layer is formed to have a variable width in the first horizontal direction along the second horizontal direction.

12. The method of claim 1 , wherein in the forming of the inner blocking layer, the inner blocking layer is formed to have a variable width in the first horizontal direction along the second horizontal direction.

13. The method of claim 1 , wherein in the forming of the outer blocking layer, the outer blocking layer is formed to include a first middle portion covering the nanosheet stack on a central portion of the fin top in the second horizontal direction,
wherein in the forming of the inner blocking layer, the inner blocking layer is formed to include a second middle portion in contact with the first middle portion, and
wherein a width of the second middle portion in the first horizontal direction is equal to or greater than a width of the first middle portion.

14. A method of manufacturing an integrated circuit device, the method comprising:
forming a stack structure including a plurality of sacrificial semiconductor layers and a plurality of nanosheet semiconductor layers alternately stacked on a fin top of a fin-type active region one by one, the fin-type active region extending lengthwise in a first horizontal direction;
forming a plurality of dummy gate structures on the stack structure of the plurality of sacrificial semiconductor layers and the plurality of nanosheet semiconductor layers;
forming a plurality of outer insulating spacers covering opposite sidewalls of each of the plurality of dummy gate structures;
forming a plurality of nanosheet stacks from the plurality of nanosheet semiconductor layers by removing portions of each of the plurality of sacrificial semiconductor layers and the plurality of nanosheet semiconductor layers using the plurality of dummy gate structures and the plurality of outer insulating spacers as an etching mask; and
forming a source/drain area between two adjacent nanosheet stacks among the plurality of nanosheet stacks on the fin-type active region, the forming of the source/drain area comprising:
forming an outer blocking layer;
forming an inner blocking layer on the outer blocking layer; and
forming a main body layer on the inner blocking layer,
wherein each of the outer blocking layer and the main body layer includes a Si 1-x Ge x layer, where x≠0, and the inner blocking layer includes a Si layer, and
wherein the inner blocking layer has a width greater than a width of the outer blocking layer.

15. The method of claim 14 , further comprising, after the forming of the plurality of nanosheet stacks, forming a recess between two adjacent nanosheet stacks among the plurality of nanosheet stacks on the fin-type active area by etching the fin-type active area,
wherein in the forming of the source/drain area, the source/drain area is formed on the recess.

16. The method of claim 15 , wherein in the forming of the recess, a level of a lowermost surface of the rec

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Minhee
• Cho Keunhwi
• Kang Myunggil
• Kim Seokhoon
• Kim Dongwon
• Park Pankwi
• Shin Dongsuk

Classifications

• H10P14/3444

  P-type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10D62/834

  further characterised by the dopants · CPC title

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title