Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same
US-2016181368-A1 · Jun 23, 2016 · US
Semiconductor device and method for fabricating the same
US10109717B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10109717-B2 |
| Application number | US-201715596152-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 16, 2017 |
| Priority date | Nov 9, 2016 |
| Publication date | Oct 23, 2018 |
| Grant date | Oct 23, 2018 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer. 2. The semiconductor device as claimed in claim 1 , wherein: the first fin includes silicon, and the first epitaxial layer and the second epitaxial layer each include silicon germanium. 3. The semiconductor device as claimed in claim 2 , wherein a germanium concentration of the first epitaxial layer is lower than a germanium concentration of the second epitaxial layer. 4. The semiconductor device as claimed in claim 1 , wherein the first epitaxial layer includes: a first portion on a bottom surface of the first trench; and a second portion on a side surface of the first trench. 5. The semiconductor device as claimed in claim 4 , wherein a thickness of the first portion is thicker than a thickness of the second portion. 6. The semiconductor device as claimed in claim 4 , wherein the second portion is in contact with the first gate electrode. 7. The semiconductor device as claimed in claim 1 , further comprising a third epitaxial layer between the second epitaxial layer and the first epitaxial layer, wherein a germanium concentration of the third epitaxial layer is lower than a germanium concentration of the second epitaxial layer. 8. The semiconductor device as claimed in claim 7 , wherein a germanium concentration of the third epitaxial layer is higher than a germanium concentration of the first epitaxial layer. 9. The semiconductor device as claimed in claim 1 , wherein an upper surface of the first epitaxial layer has a U shape in cross section. 10. The semiconductor device as claimed in claim 1 , further comprising a first gate spacer on a sidewall of the first gate electrode, wherein the first trench is in contact with a lower surface of the first gate spacer.
Assignees
Inventors
Classifications
- H01L29/4236Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US10109717B2 cover?
- A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer be…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H01L29/4236. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Oct 23 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).