MOS devices with non-uniform P-type impurity profile

Patent metadata

Field	Value
Publication number	US-9601619-B2
Application number	US-201313943517-A
Country	US
Kind code	B2
Filing date	Jul 16, 2013
Priority date	Jul 16, 2013
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A silicon germanium region is disposed in the opening, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.

First claim

What is claimed is:

1. A method comprising:
forming a gate stack over a semiconductor substrate;
forming an opening extending into the semiconductor substrate, wherein the opening is on a side of the gate stack;
performing a first epitaxy to grow a first silicon germanium region in the opening, wherein during the first epitaxy, the first silicon germanium region is in-situ doped to a first p-type impurity concentration; and
performing a second epitaxy to grow a silicon cap substantially free from germanium over the first silicon germanium region, wherein during the second epitaxy, the silicon cap is in-situ doped to a second p-type impurity concentration higher than the first p-type impurity concentration.

2. The method of claim 1 further comprising, before the first epitaxy, performing a third epitaxy to grow a second silicon germanium region underlying the first silicon germanium region, with the second silicon germanium region having a higher germanium percentage than the first silicon germanium region, wherein during the third epitaxy, the second silicon germanium region is in-situ doped to a third p-type impurity concentration lower than the first p-type impurity concentration.

3. The method of claim 1 further comprising, before the first epitaxy, performing a third epitaxy to grow a second silicon germanium region underlying the first silicon germanium region, wherein during the third epitaxy, substantially no p-type impurity is doped.

4. The method of claim 1 , wherein a ratio of the second p-type impurity concentration to the first p-type impurity concentration is higher than about 10.

5. The method of claim 1 , wherein during the second epitaxy, no germanium is introduced into the silicon cap.

6. The method of claim 1 further comprising:
after forming the silicon cap, forming an Inter-Layer Dielectric (ILD) over the gate stack and the silicon cap;
forming a contact opening in the ILD, wherein the silicon cap is exposed to the contact opening;
after the contact opening is formed, performing a silicidation on the silicon cap; and
filling the contact opening with a conductive material.

7. The method of claim 6 , wherein after the silicidation, a portion of the silicon cap remains un-silicided, and wherein during the silicidation, a portion of the first silicon germanium region is silicided.

8. A method comprising:
forming a gate stack over a semiconductor substrate;
etching the semiconductor substrate to form an opening adjacent to the gate stack;
performing a first epitaxy to grow a silicon germanium region in the opening; and
performing a second epitaxy to grow a silicon cap over the silicon germanium region, wherein during the second epitaxy, the silicon cap is in-situ doped to a p-type impurity concentration higher than p-type impurity concentrations of all epitaxy regions in the opening.

9. The method of claim 8 , wherein the gate stack forms an interface with a top surface of the semiconductor substrate, and the silicon cap is higher than the interface.

10. The method of claim 8 , wherein the silicon cap is free from germanium.

11. The method of claim 8 , wherein the first epitaxy further comprises:
performing a third epitaxy to grow a first silicon germanium region in the opening, wherein during the third epitaxy, the first silicon germanium region is not in-situ doped with p-type impurities; and
performing a fourth epitaxy to grow a second silicon germanium region over the first silicon germanium region, wherein the second silicon germanium region is in-situ doped during the fourth epitaxy.

12. The method of claim 8 , wherein the first epitaxy further comprises:
performing a third epitaxy to grow a first silicon germanium region in the opening, wherein during the third epitaxy, the first silicon germanium region is in-situ doped to a first p-type impurity concentration; and
performing a fourth epitaxy to grow a second silicon germanium region over the first silicon germanium region, wherein the second silicon germanium region is in-situ doped to a second p-type impurity concentration higher than the first p-type impurity concentration.

13. The method of claim 12 , wherein a ratio of the second p-type impurity concentration to the first p-type impurity concentration is higher than about 10.

14. The method of claim 8 further comprising:
siliciding a middle portion of the silicon cap to form a silicide region, wherein after the siliciding, the silicon cap comprises portions remaining on opposite sides of the silicide region.

15. The method of claim 14 , wherein during the siliciding, a top portion of the silicon germanium region is silicided.

16. A method comprising:
forming a gate stack over a semiconductor substrate, with the gate stack forming an interface with a portion of the semiconductor substrate directly underlying the gate stack;
etching the semiconductor substrate to form an opening adjacent to the gate stack;
performing a first epitaxy to grow a first semiconductor region in the opening, with a top surface of the first semiconductor region higher than the interface, wherein during the first epitaxy, the first semiconductor region is in-situ doped to have a first p-type impurity concentration; and
performing a second epitaxy to grow a second semiconductor region overlying the first semiconductor region, wherein during the second epitaxy, the second semiconductor region is in-situ doped to a second p-type impurity concentration higher than the first p-type impurity concentration.

17. The method of claim 16 , wherein the second semiconductor region is a silicon cap free from germanium.

18. The method of claim 16 further comprising:
performing a third epitaxy to grow a third semiconductor region in the opening, wherein during the third epitaxy, no p-type impurity is in-situ doped, and the third semiconductor region is underlying the first semiconductor region.

19. The method of claim 16 further comprising:
siliciding a top portion of the second semiconductor region, wherein a bottom portion of the second semiconductor region directly underlying the top portion is not silicided.

20. The method of claim 16 further comprising:
siliciding a portion of the second semiconductor region and a portion of the first semiconductor region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Sung Hsueh-Chang
• Kwok Tsz-Mei
• Li Kun-Mu
• Lee Tze-Liang
• Li Chii-Horng

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title