Nanowire transistor with underlayer etch stops

Patent metadata

Field	Value
Publication number	US-9064944-B2
Application number	US-201313996848-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Jun 23, 2015
Grant date	Jun 23, 2015

Abstract

A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.

First claim

What is claimed is:

1. A nanowire transistor, comprising:
at least one nanowire channel having a first end, and an opposing second end, wherein the at least one nanowire channel is disposed over a microelectronic substrate;
a source structure proximate the at least one nanowire first end, wherein a first underlayer etch stop structure is disposed between the source structure and the at least one nanowire first end and disposed between the entire source structure and the microelectronic substrate; and
a drain structures proximate the at least one nanowire second end, wherein a second underlayer etch stop structure is disposed between the drain structure and the at least one nanowire second end and disposed between the entire drain structure and the microelectronic substrate.

2. The nanowire transistor of claim 1 , further including a gate dielectric material abutting the nanowire channel between the nanowire channel first end and the nanowire channel second end.

3. The nanowire transistor of claim 2 , further including a gate electrode material abutting the gate dielectric material.

4. The nanowire transistor of claim 1 , wherein the nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure are the same material.

5. The nanowire transistor of claim 4 , wherein the nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure are silicon germanium.

6. The nanowire transistor of claim 4 , wherein the nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure are silicon.

7. The nanowire transistor of claim 1 , wherein the at least one nanowire channel comprises a plurality of nanowires channels formed above the microelectronic substrate, wherein the nanowire channels are spaced apart from one another.

8. A computing device, comprising:
a board including at least one component;
wherein the at least one component includes at least one microelectronic structure comprising at least one nanowire transistor including at least one nanowire channel having a first end, and an opposing second end, wherein the at least one nanowire channel is disposed over a microelectronic substrate; a source structure proximate the at least one nanowire first end, wherein a first underlayer etch stop structure is disposed between the source structure and the at least one nanowire first end and disposed between the entire source structure and the microelectronic substrate; and a drain structures proximate the at least one nanowire second end, wherein a second underlayer etch stop structure is disposed between the drain structure and the at least one nanowire second end and disposed between the entire drain structure and the microelectronic substrate.

9. The computing device of claim 8 , further including a gate dielectric material abutting the nanowire channel between the nanowire channel first end and the nanowire channel second end.

10. The computing device of claim 9 , further including a gate electrode material abutting the gate dielectric material.

11. The computing device of claim 8 , wherein the nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure are the same material.

12. The computing device of claim 11 , wherein the nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure are silicon germanium.

13. The computing device of claim 11 , wherein the nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure are silicon.

14. The computing device of claim 8 , wherein the at least one nanowire channel comprises a plurality of nanowires channels formed above the microelectronic substrate, wherein the nanowire channels are spaced apart from one another.

Assignees

• Kim Seiyon
• Aubertine Daniel
• Kuhn Kelin
• Murthy Anand
• Intel Corp

Inventors

• Kim Seiyon
• Aubertine Daniel
• Kuhn Kelin
• Murthy Anand

Classifications

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/292

  Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512) · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title