Integrated circuit including standard cell and filler cell

Patent metadata

Field	Value
Publication number	US-12230625-B2
Application number	US-202418591089-A
Country	US
Kind code	B2
Filing date	Feb 29, 2024
Priority date	Mar 26, 2021
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

An integrated circuit includes a standard cell including a first active region extending in a first direction and having a first width, and a filler cell including a second active region of a same type as that of the first active region and being adjacent to the standard cell in the first direction, the second active region extending in the first direction and having a second width which is greater than the first width, wherein the standard cell further includes a first tapering portion of the same type as that of the first active region, the first tapering portion being arranged between the first active region and the second active region.

First claim

What is claimed is:

1. An integrated circuit comprising:
a standard cell comprising a first active region extending in a first direction and having a first width; and
a filler cell comprising a second active region of a same type as that of the first active region and being adjacent to the standard cell in the first direction, the second active region extending in the first direction and having a second width which is greater than the first width,
wherein the standard cell further comprises a first tapering portion of the same type as that of the first active region, the first tapering portion being arranged between the first active region and the second active region and comprising a first contact surface contacting the first active region in the first direction, a second contact surface contacting the second active region in the first direction, and an inclination surface connecting the first contact surface to the second contact surface and having an inclination.

2. The integrated circuit of claim 1 ,
wherein the filler cell further comprises a third active region of a different type from that of the second active region, the third active region being spaced apart from the second active region in a second direction perpendicular to the first direction, extending in the first direction, and having the second width,
wherein the standard cell further comprises:
a fourth active region of a same type as that of the third active region, the fourth active region being spaced apart from the first active region in the second direction, extending in the first direction, and having the first width; and
a second tapering portion of the same type as that of the third active region, the second tapering portion being arranged between the third active region and the fourth active region and comprising a first surface contacting the fourth active region in the first direction, a second surface contacting the third active region in the first direction, and a third surface connecting the first surface to the second surface and having an inclination, and

wherein a distance between the first tapering portion and the second tapering portion decreases toward the filler cell.

3. The integrated circuit of claim 1 ,
wherein the filler cell further comprises a third active region of a different type from that of the second active region, the third active region being spaced apart from the second active region in a second direction perpendicular to the first direction, extending in the first active region, and having a third width which is less than the second width,
wherein the standard cell further comprises a fourth active region of a same type as that of the third active region, the fourth active region being spaced apart from the first active region in the second direction, extending in the first direction, and having the third width, and
wherein a distance between the fourth active region and the first tapering portion decreases toward the filler cell.

4. The integrated circuit of claim 3 , wherein the third width is the same as the first width.

5. The integrated circuit of claim 1 ,
wherein the filler cell further comprises a third active region of a different type from that of the second active region, the third active region being spaced apart from the second active region in a second direction perpendicular to the first direction, extending in the first active region, and having the second width,
wherein the standard cell further comprises:
a fourth active region of a same type as that of the third active region, the fourth active region being spaced apart from the first active region in the second direction, extending in the first direction, and having the first width; and
a second tapering portion of the same type as that of the third active region, the second tapering portion being arranged between the third active region and the fourth active region and comprising a first surface contacting the fourth active region in the first direction, a second surface contacting the third active region in the first direction, and a third surface connecting the first surface to the second surface and having an inclination, and

wherein a distance between the first tapering portion and the second tapering portion is constant.

6. The integrated circuit of claim 1 ,
wherein the filler cell further comprises a third active region of a different type from that of the second active region, the third active region being spaced apart from the second active region in a second direction perpendicular to the first direction, extending in the first active region, and having a third width which is less than the second width,
wherein the standard cell further comprises a fourth active region of a same type as that of the third active region, the fourth active region being spaced apart from the first active region in the second direction, extending in the first direction, and having the third width, and
wherein a distance between the fourth active region and the first tapering portion is constant.

7. The integrated circuit of claim 6 , wherein the third width is the same as the first width.

8. The integrated circuit of claim 1 , wherein the inclination surface comprises a straight line or a curved line.

9. The integrated circuit of claim 1 , wherein the filler cell further comprises a contact connected to the second active region.

10. The integrated circuit of claim 1 , wherein the standard cell further comprises a gate-all-around transistor formed in the first active region.

11. An integrated circuit comprising:
a standard cell comprising a first active region extending in a first direction and having a first width; and
a filler cell comprising a second active region of a same type as that of the first active region and being adjacent to the standard cell in the first direction, the second active region extending in the first direction and having a second width which is less than the first width,
wherein the standard cell further comprises a first reverse tapering portion of the same type as that of the first active region, the first reverse tapering portion being arranged between the first active region and the second active region and comprising a first contact surface contacting the first active region in the first direction, a second contact surface contacting the second active region in the first direction, and an inclination surface connecting the first contact surface to the second contact surface and having an inclination.

12. The integrated circuit of claim 11 ,
wherein the filler cell further comprises a third active region of a different type from that of the second active region, the third active region being spaced apart from the second active region in a second direction perpendicular to the first direction, extending in the first direction, and having the second width,
wherein the standard cell further comprises:
a fourth active region of the same type as that of the third active region, the fourth active region being spaced apart from the first active region in the second direction, extending in the first direction, and having the first width; and
a second reverse tapering portion of the same type as that of the third active region, the second reverse tapering portion being arranged between the third active region and the fourth active region and comprising a first surface contacting the fourth active region in the first direction, a second surface contacting the third active region in the first direction, and a third surface connecting the first surface to the second surface and having an inclination, and

wherein a distance between the first reverse tapering portion and

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Hakchul
• Kim Ingyum
• Yang Giyoung
• Seo Jaewoo

Classifications

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D84/907

  CMOS gate arrays · CPC title

• H10D84/974

  Layout specifications, i.e. inner core regions · CPC title